US4872045A
Expired / Lapsed
US
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Input protection device for C-MOS device
Assignee: Toshiba Corp
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Filing: 1983-09-02
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Granted: 1989-10-03
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Expires: 2003-09-02
Abstract
Abstract An input protection device for a C-MOS device having an n-type semiconductor substrate and a p-type well region. The device comprises a diode consisting of the p-type well region and an n + -type layer diffusion formed in the p-type well region and connected between a gate of a C-MOS FET and ground. The n + -type layer of the diode has a higher impurity concentration and a greater diffusion depth than those of n + -type layers formed in the p-type well region and constitute the source and drain of an n-channel MOSFET.
Inventors
- 👤 Isao Baba
- 👤 Takeo Kondo
- 👤 Leiichi Yanagisawa
- 👤 Kenji Kohguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:56
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
167 words
An input protection device for a C-MOS device comprising: an n-type semiconductor substrate; a p-type well region formed in a surface region of said n-type semiconductor substrate; first n-type layers formed in a surface region of said p-type well region, serving as a source and drain of an n-channel MOSFET; a second n-type layer formed in the surface region of said p-type well region, serving as a cathode of a diode having a single PN junction, the impurity concentration of said second n-type layer being higher than the impurity concentration of said first n-type layer; p-type layers formed in the surface region of said n-type substrate, serving as a source and drain of a p-channel MOSFET; a first n + -type polysilicon layer formed on said n-type semiconductor substrate; and a first insulating film isolating said first n + -type polysilicon layer from said substrate; said first n + -type polysilicon layer having one end connected to said second n-type layer and serving as a protection resistor.
Claim 2
Dependent Claim
167 words
An input protection device for a C-MOS device comprising: an n-type semiconductor substrate; a p-type well region formed in a surface region of said n-type semiconductor substrate; first n-type layers formed in a surface region of said p-type well region, serving as a source and drain of an n-channel MOSFET; a second n-type layer formed in the surface region of said p-type well region, serving as a cathode of a diode having a single PN junction, the impurity concentration of said second n-type layer being higher than the impurity concentration of said first n-type layer; p-type layers formed in the surface region of said n-type substrate, serving as a source and drain of a p-channel MOSFET; a first n + -type polysilicon layer formed on said n-type semiconductor substrate; and a first insulating film isolating said first n + -type polysilicon layer from said substrate; said first n + -type polysilicon layer having one end connected to said second n-type layer and serving as a protection resistor.
Claim 3
Dependent Claim
27 words
An input protection device according to claim 1, wherein said second n-type layer has a greater diffussion depth than the diffusion depth of said first n-type layers.
Claim 4
Dependent Claim
19 words
An input protection device according to claim 1, wherein said second n-type layer is formed through two diffusion steps.
Claim 5
Dependent Claim
24 words
An input protection device according to claim 1, wherein the resistance of said n + -type polysilicon layer is not higher than 1.5 kΩ.
Claim 6
Dependent Claim
46 words
An input protection device according to claim 1, wherein the ON resistance of a diode which is reverse biased and is constituted by said p-type well region and second n-type layer is not higher than one-fourth of the resistance of said n + -type polysilicon layer.
Claim 7
Dependent Claim
23 words
An input protection device according to claim 1, wherein a thickness of a gate oxide film of said n-channel MOSFET is 800 Å.
Claim 8
Dependent Claim
89 words
An input protection device according to claim 1, further comprising: a second insulating film formed on said n-type semiconductor substrate and on said p-type well region; second n + -type polysilicon layers formed on said second insulating film on said n-type semiconductor substrate and said p-type well region, said second n + -type polysilicon layers serving as gate electrodes of said p-channel MOSFET and said n-channel MOSFET, each of said second n + -type polysilicon layers having a first end connected to said first n + -type polysilicon layer.
Claim 9
Dependent Claim
35 words
An input protection device according to claim 1, wherein a ratio of ON resistance of said diode to a resistane of said first n + -type polysilicon layer is not greater than 1 : 4.
Claim 10
Dependent Claim
42 words
An input protection device according to claim 1, wherein said p-type well region is connected to a ground terminal and wherein said first n + -type polysilicon layer comprises a second end adapted to receive an input signal to the C-MOS device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |