FSK demodulation circuit

Claim 1

A frequency shift keying (FSK) demodulation circuit having: phase detection means which receives as an input an FSK modulated reception signal and performs phase detection on the same so as to produce quadrature I-ch and Q-ch analog base band signals and which further converts said analog base band signals to digital signals and outputs a first pulse train and a second pulse train, respectively, and data reproducing means which reproduces the original data from the first pulse train and the second pulse train to output reproduced data, said data reproducing means comprising: first sampling means which uses an edge of the second pulse train and samples the logic of the first pulse train to obtain a first sample output; second sampling means which uses an edge of the first pulse train and samples the inverted logic of the second pulse train to obtain a second sample output, said first and second sampling means using the edges of the second and first pulse trains, respectively, for sampling the logics at mutually different timings; decision means which receives as inputs the sample outputs from said first and second sampling means and determines the logic of said reproduced data by a predetermined decision operation on the sample outputs, said decision means including a coincidence detection part which detects coincidence or noncoincidence of the logic levels of said first and second sample outputs and a latch circuit which forms the logic level of said reproduced data using the current logic level upon coincidence and forms the logic level of said reproduced data with the logic level just before, held internally, upon noncoincidence; and delay means for applying a predetermined delay to said first sample output and applying the delayed first sample output to said latch circuit, said delay means providing a delay time set substantially equal to the time required for detection of coincidence at said coincidence detection part.