Procedure and circuit for detection of the information of a received signal

Claim 2

Method for detecting binary information in a received signal, comprising initially demodulating said received signal into a first quadrature signal and a second quadrature signal which is phase shifted by 90 degrees, converting each of said first and second quadrature signals into a sequence of samples corresponding to the amplitude and polarity of the associated quadrature signal at instant of the sampling, whereby the instant of the sampling is controlled dependent on the crossover of the other quadrature signal in each case; inverting or non-inverting the polarity of the samples obtained, dependent upon the directions of the crossovers of the other quadrature signal in each case; whereby the inversion of samples of the first quadrature signal and the inversion of the samples of the second quadrature signal occurs, in each case, at opposite directions of the crossovers of the second quadrature signal and the first quadrature signal, to generate samples with adapted polarities within each individual information bit interval of the received signal from both quadrature signals; summing all samples with adapted polarities within each individual information bit interval of the received signal, and evaluating the preceding sign of the resulting sum as an estimate of the received binary information symbol.

Claim 3

Method according to claim 1, wherein the amount of the resulting sum of all samples with adapted polarities within an information-bit interval of the received signal is evaluated as the standard of quality of the estimate of the received binary information symbol.

Claim 4

Electrical circuit for detecting binary information in a received signal, comprising circuit elements for demodulating a received signal into a first quadrature signal and a second quadrature signal which is phase-shifted by 90 degrees from said first quadrature signal, conversion means for converting each of the quadrature signals into a sequence of samples, corresponding to the amplitude and polarity of the quadrature signal existing at the instant of the sampling; means for controlling the instants of the sampling, dependent on the crossover through zero of the other quadrature signal in each case; means for inverting a portion of the samples obtained dependent on the directions of the crossovers through zero of the other quadrature signal in each case, such that the inversion of the samples of the first quadrature signal occurs, in each case, at oppositie directions of the crossovers through zero of the second quadrature signal and the first quadrature signal, to generate within each individual information bit interval of the received signal, samples with adapted polarities, from both quadrature signals; means for adding all samples with adapted polarities within each individual bit interval algebraicially; and means to generate an output signal which signals have the preceding sign of each resulting sum, which represents an estimate of the received binary information symbol.

Claim 5

Electrical circuit for detecting binary information in a received signal, comprising circuit elements for demodulating a received signal into a first quadrature signal and a second quadrature signal which is phase-shifted by 90 degrees from said first quadrature signal, conversion means for converting each of the quadrature signals into a sequence of samples, corresponding to the amplitude and polarity of the quadrature signal existing at the instant of the sampling; means for controlling the instants of the sampling, dependent on the crossover through zero of the other quadrature signal in each case; means for inverting a portion of the samples obtained dependent on the directions of the crossovers through zero of the other quadrature signal in each case, such that the inversion of the samples of the first quadrature signal occurs, in each case, at oppositie directions of the crossovers through zero of the second quadrature signal and the first quadrature signal, to generate within each individual information bit interval of the received signal, samples with adapted polarities, from both quadrature signals; means for adding all samples with adapted polarities within each individual bit interval algebraicially; and means to generate an output signal which signals have the preceding sign of each resulting sum, which represents an estimate of the received binary information symbol.

Claim 6

Circuit according to claim 3, wherein the means for converting each quadrature signal into a sequence of samples are instantaneous value samples for sampling the first and second quadrature signals, respectively, and means for controlling the instants of the sampling are two crossover detectors for ascertaining the crossovers through zero of the first and second quadrature signals, respectively, whereby the control signals generated by the crossovers of the first quadrature signal are passed to the instantaneous value sampler for the second quadrature signal, to control the instantaneous value sampler, and the control signals generated by the crossovers of the second quadrature signal are passed to the instantaneous value sampler for the first quadrature signal, to control the latter-mentioned instantaneous value sampler.

Claim 7

Circuit according to claim 4, wherein the means for inverting a portion of the samples include two polarity inverters controllable by control signals, for the samples of the first quadrature signal, and the samples of the second quadrature signal, respectively; and the crossover detectors generate a control singal for the polarity inverters, dependent upon the direction of the crossovers through zero of the second and first quadrature signals, respectively.

Claim 8

Circuit according to claim 3, wherein the means for algebraic adding of the samples with adapted polarities is an adder controllable by a timing signal, with entries for the samples derived from the first and second quadrature signal, respectively, and with an output for the output signal which indicates the polarity of each sum; and means for generation of the timing signal in correspondence with the instants of the beginning and the end of each information bit interval of the binary information of the received signal.

Claim 9

Circuit according to claim 3, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.

Claim 10

Circuit according to claim 4, wherein the means for algegraic adding of the samples with adapted polarities is an adder controllable by a timing signal, with entries for the samples derived from the first and second quadrature signal, respectively, and with an output for the output signal which indicates the polarity of each sum; and means for generation of the timing signal in correspondence with the instants of the beginning and the end of each information bit interval of the binary information of the received signal.

Claim 11

Circuit according to claim 5, wherein the means for algebraic adding of the samples with adapted polarities is an adder controllable by a timing signal, with entries for the samples derived from the first and second quadrature signal, respectively, and with an output for the output signal which indicates the polarity of each sum; and means for generation of the timing signal in correspondence with the instants of the beginning and the end of each information bit interval of the binary information of the received signal.

Claim 12

Circuit according to claim 4, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.

Claim 13

Circuit according to claim 5, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.

Claim 14

Circuit according to claim 6, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.

Claim 15

Circuit according to claim 8, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.

Claim 16

Circuit according to claim 9, wherein the means for algebraic addition of the samples with adapted polarities also generate a second output signal which indicates the amount of the resulting sum in each case and represents the quality of the estimate of the received binary information symbol.