Patent US4870355A successfully refreshed from Google Patents.
US4870355A
Expired / Lapsed
US
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Thermal fixture for testing integrated circuits
Assignee: Thermonics Inc
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Filing: 1988-09-09
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Granted: 1989-09-26
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Expires: 2008-09-09
Abstract
Abstract A device for individually testing semiconductor integrated circuits in wafer form at elevated and/or reduced temperatures include a fixture body for connection to a conventional probing device. The fixture body has an open-ended aperture to permit visual inspection of a circuit being tested, a plenum to receive pressurized gas at a selected temperature(s), and nozzles to direct the gas from the plenum into the aperture for ejection onto to the surface of the integrated circuit being tested to rapdily bring that circuit to the temperature of the gas.
Inventors
- 👤 James C. Kufis
- 👤 Robert S. Semken
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 13:48
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/2872; G01R31/2874; G01R31/286; G01R31/2863
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
145 words
A method for individually testing integrated circuits which are part of a semiconductor wafer, said method comprising the steps of: positioning the semiconductor wafer to bring an individual integrated circuit to be tested into electrical contact with a probing means; viewing the individual integrated circuit being tested through an aperture; directing a flow of pressurized gas through the viewing aperture to impinge upon the individual integrated circuit being tested to bring the temperature of that circuit substantially equal to the temperature of the gas; electrically testing the individual integrated circuit at the gas temperature while simultaneously viewing the circuit through the aperture; varying the temperature of the gas to bring the temperature of the individual circuit being tested to different test temperatures while in the same position; and sequentially positioning individual integrated circuits of the wafer in alignment with the probing means and the aperture.
Claim 2
Independent Claim
145 words
A method for individually testing integrated circuits which are part of a semiconductor wafer, said method comprising the steps of: positioning the semiconductor wafer to bring an individual integrated circuit to be tested into electrical contact with a probing means; viewing the individual integrated circuit being tested through an aperture; directing a flow of pressurized gas through the viewing aperture to impinge upon the individual integrated circuit being tested to bring the temperature of that circuit substantially equal to the temperature of the gas; electrically testing the individual integrated circuit at the gas temperature while simultaneously viewing the circuit through the aperture; varying the temperature of the gas to bring the temperature of the individual circuit being tested to different test temperatures while in the same position; and sequentially positioning individual integrated circuits of the wafer in alignment with the probing means and the aperture.
Claim 3
Dependent Claim
23 words
The method of claim 1 wherein, said gas is clean, dry nitrogen at selectable temperatures of about 0°-55° C., ambient, and +150° C.
References Cited (Backward Citations)
US3710251A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-25 | 1993-03-27 | 1993-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-25 | 1997-03-27 | 1997-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-25 | 2001-03-27 | 2001-09-26 | $7700.00 | Window Closed / Lapsed |