GaAs capacitive feedback transimpedance amplifier

Claim 2

A capacitive feedback transimpedance amplifier integrated circuit comprising: means, having an input terminal for coupling to an output signal of an IR detector, for amplifying said detector output signal to produce at an output terminal an amplifier output signal; means, coupled to said input terminal, for periodically coupling said input terminal to a first predetermined voltage potential; means, coupled to said output terminal, for periodically coupling said output terminal to a second predetermined voltage potential; and means, coupled between said output terminal and said input terminal, for feeding back to said input terminal a feedback signal having a magnitude linearly related to a magnitude of said amplifier output signal.

Claim 3

A capacitive feedback transimpedance amplifier as defined in claim 1 wherein said means for feeding back comprises: a buffer amplifier having a buffer amplifier input terminal coupled to said output terminal, said buffer amplifier further having a buffer amplifier output terminal; and a capacitor having a first terminal coupled to said buffer amplifier output terminal and a second terminal coupled to said amplifier input terminal for coupling said feedback signal from said buffer amplifier output terminal to said input terminal.

Claim 4

A capacitive feedback transimpedance amplifier as defined in claim 2 wherein said amplifying means comprises: a differential amplifier comprising a first and a second amplifier transistor connected in parallel one to another, each having a source terminal coupled to an output of a current source means, said first amplifier transistor having a gate terminal for coupling to said radiation detector output signal, said second amplifier transistor having a gate terminal coupled to a circuit ground, each of said first and second amplifier transistors first and a second load means, respectively.

Claim 5

A capacitive feedback transimpedance amplifier as defined in claim 3 wherein said first load means comprises two serially coupled load transistors disposed between said drain terminal of said first amplifier transistor and a voltage source, said first load transistor comprising: a source terminal coupled to said drain terminal of said first amplifier transistor, a drain terminal coupled to a source and a gate terminal of said second load transistor and also to said buffer amplifier input terminal, and a gate terminal coupled to said second load means and also to a first variable voltage potential having a predetermined magnitude for adjusting the current flow through said first and said second amplifier transistors to achieve a desired voltage potential at said drain of each of said amplifier transistors.

Claim 6

A capacitive feedback transimpedance amplifier as defined in claim 4 wherein said current source means comprises: a current sourcing transistor having a source terminal coupled to said circuit ground, a drain terminal coupled to said source terminals of said first and said second amplifier transistors, and a gate terminal coupled to a second variable voltage potential having a predetermined magnitude for adjusting the current flow through said first and second amplifier transistors.

Claim 7

A capacitive feedback transimpedance amplifier as defined in claim 2 and further comprising: means for storing a charge signal having a magnitude linearly related to a magnitude of said radiation detector output signal; means, coupled between said buffer amplifier output terminal and said storing means, for periodically impressing upon said storing means said charge signal; and means, coupled to said storing means, for periodically outputting a voltage signal having a magnitude linearly related to the magnitude of said radiation detector output signal.

Claim 8

A capacitive feedback transimpedance amplifier as defined in claim 6 wherein said transimpedance amplifier is comprised of GaAs and wherein said impressing means is a MISFET GaAs transistor having a drain and a source terminal coupled between said buffer amplifier output terminal and said storing means, said MISFET GaAs transistor further having a gate terminal coupled to a clock signal which periodically causes said MISFET GaAs transistor to conduct thereby impressing upon said storing means said buffer amplifier output signal.

Claim 11

A method as defined in claim 8 wherein while the steps (a)-(g) are accomplished further includes a step of feeding back the output signal of the transimpedance amplifier to the input of the transimpedance amplifier through a feedback capacitor.

Claim 12

A method as defined in claim 9 wherein the step of reading out the initial magnitude is accomplished substantially immediately before the step of sampling the final magnitude.

Claim 13

A method as defined in claim 10 wherein the CTIA is comprised of GaAs transistors and wherein the steps of sampling are accomplished by energizing a MISFET GaAs transistor to couple the amplifier output signal to a sample and hold storage capacitor.

Claim 14

A method as defined in claim 10 and further comprising a step of subtracting the initial magnitude of the output signal from the final magnitude of the output signal whereby at least a 1/f noise component of the output signal is substantially cancelled.

Claim 15

A method as defined in claim 10 wherein the CTIA is comprised of MESFET, HEMT, SDHT or MODFET transistors and wherein the steps of sampling are accomplished by energizing a MISFET GaAs transistor to couple the amplifier output signal to a sample and hold storage capacitor.

Claim 16

A radiation detector readout integrated circuit for use at cryrogenic temperatures having a plurality of transistor devices comprised of GaAs, said circuit comprising: an input stage, said input stage comprising a differential amplifier including a first and a second amplifier transistor connected in parallel one to another, each having a source terminal coupled to an output of a current source transistor, said first amplifier transistor having a gate terminal for coupling to a radiation detector output signal, said second amplifier transistor having a gate terminal coupled to a circuit ground, each of said first and second amplifier transistors further having a drain terminal coupled to a first and a second load means, respectively; a first switching transistor coupled between said gate terminal of said first amplifier transistor and a first voltage potential, said first switching transistor further having a gate terminal coupled to a first clock signal for periodically coupling said first amplifier transistor gate terminal to the first voltage potential; a second switching transistor coupled between an output of said input stage and a second voltage potential, said second switching transistor further having a gate terminal coupled to a second clock signal for periodically coupling said output of said input stage to the second voltage potential; and an output stage comprising a buffer amplifier having a buffer amplifier input terminal coupled to said output of said input stage, said buffer amplifier further having a buffer amplifier output terminal; a first capacitor having a first terminal coupled to said buffer amplifier output terminal and a second terminal coupled to said gate terminal of said first amplifier transistor for feeding back a signal from said buffer amplifier output terminal to said gate terminal of said first amplifier transistor; a MISFET transistor having a drain and a source terminal coupled between said buffer amplifier output terminal and a second capacitor, said MISFET transistor further having a gate terminal coupled to a third clock signal which periodically causes said MISFET transistor to conduct thereby impressing upon said second capacitor said buffer amplifier output signal; and an output transistor having a gate terminal coupled to said second capacitor and a source terminal coupled to a fourth clock signal for periodically outputting a signal having a magnitude which is a function of a magnitude of the radiation detector output signal.

Claim 17

A radiation detector readout integrated circuit for use at cryrogenic temperatures having a plurality of transistor devices comprised of GaAs, said circuit comprising: an input stage, said input stage comprising a differential amplifier including a first and a second amplifier transistor connected in parallel one to another, each having a source terminal coupled to an output of a current source transistor, said first amplifier transistor having a gate terminal for coupling to a radiation detector output signal, said second amplifier transistor having a gate terminal coupled to a circuit ground, each of said first and second amplifier transistors further having a drain terminal coupled to a first and a second load means, respectively; a first switching transistor coupled between said gate terminal of said first amplifier transistor and a first voltage potential, said first switching transistor further having a gate terminal coupled to a first clock signal for periodically coupling said first amplifier transistor gate terminal to the first voltage potential; a second switching transistor coupled between an output of said input stage and a second voltage potential, said second switching transistor further having a gate terminal coupled to a second clock signal for periodically coupling said output of said input stage to the second voltage potential; and an output stage comprising a buffer amplifier having a buffer amplifier input terminal coupled to said output of said input stage, said buffer amplifier further having a buffer amplifier output terminal; a first capacitor having a first terminal coupled to said buffer amplifier output terminal and a second terminal coupled to said gate terminal of said first amplifier transistor for feeding back a signal from said buffer amplifier output terminal to said gate terminal of said first amplifier transistor; a MISFET transistor having a drain and a source terminal coupled between said buffer amplifier output terminal and a second capacitor, said MISFET transistor further having a gate terminal coupled to a third clock signal which periodically causes said MISFET transistor to conduct thereby impressing upon said second capacitor said buffer amplifier output signal; and an output transistor having a gate terminal coupled to said second capacitor and a source terminal coupled to a fourth clock signal for periodically outputting a signal having a magnitude which is a function of a magnitude of the radiation detector output signal.

Claim 18

A circuit as set forth in claim 14 wherein said current source transistor has a source terminal coupled to circuit ground, a drain terminal coupled to said source terminals of said first and said second amplifier transistors, and a gate terminal coupled to a first source of bias voltage potential.

Claim 19

A circuit as set forth in claim 15 wherein said load means comprises a first load transistor coupled to the drain of said first amplifier transistor and a second load transistor coupled to the drain of said second amplifier transistor, each of said first and second load transistors having a gate terminal coupled to a second source of bias voltage potential.