Memory circuit for graphic images

Claim 2

A memory circuit formed on an LSI device, comprising: (a) memory means for effecting data read, data write and store data operations, and having input means, output means and a plurality of storage locations for storing data; and (b) control means having an output connected to said input means of said memory means, and including first data input means, second data input means, third data input means, said second data input means being connected to receive data form said output means of said memory means, and controlling means operating in a first mode to a write data input from said first data input means into said memory means in response to a first value of data received from said third data input means, and operating a second mode to transfer data received from said output means of said memory means via said second data input means to said memory means in inverted form in response to a combination of a first value of data input from said first data input means and a second value of data input from said third data input means and to transfer data received from said output means of memory means via said second data input means to said memory means without modification in response to a combination of a second value of data input from said first data input means and a second value of data input from said third data input means.

Claim 3

A memory circuit according to claim 1, wherein said controlling means includes first gate means for gating inputs from said second and third data input means effective to write said data input from said first data input means into said memory and second gate means for gating data input from said first data input means and the output of said first gate means for selectively inverting the data transferred to said memory means according to the value of the data from said first data input means.

Claim 4

A memory circuit according to claim 1, further comprising addressing means for addressing a storage location of said memory means where there is stored data to be read out to said output means.

Claim 5

A memory circuit according to claim 2, further comprising first selector means and second selector means each for selecting data items from a plurality of data inputs; means for applying an output from said first selector means to said first data input means; means for applying an output from said second selector means to said third data input means; and means for independently controlling said first and second selector means for performing a respective select operation.

Claim 6

A memory circuit according to claim 4, wherein said first and second selector means each are provided with four inputs; said four inputs including a fixed logic value "0", a fixed logic value "1", a fourth data input the value of which can be arbitrarily changed to be a logic value "0" or "1", and an inverted value obtained by inverting said fourth data input; and said means for independently controlling first and second selector means operating to select one of said four inputs so as to combine the data of said first and third data input means outputted from said selectors, thereby effecting dyadic logic operation.

Claim 7

A memory circuit according to claim 1, further comprising: third selector means for selecting either data from output means of said memory means or said fourth data from an external device in response to a priority control signal; and priority control circuit means from which a priority control signal for controlling said selector is extracted by use of said data from said output means of said memory means, said fourth data from the external device, and a priority specification signal.

Claim 8

A memory circuit according to claim 6, wherein: said fourth data from the external device and said data from the output means of said memory means are subdivided in said memory means into two regions comprising a section having data which is actually to be stored and another section; said priority control circuit means includes means for controlling said selector means to select said fourth data from the external device when said priority specification signal specifies said fourth data in a processing of said region in which said fourth data from the external device and said data from the output means of said memory means are to be actually stored, to control the selector means to select data from the output means when said priority specification signal specifies said data from the output means in said processing, to control said selector means to select said data from the output means in a processing of a region in which neither said fourth data nor said data from the output means are to be actually stored, to control said selector means to select said fourth data in a processing of a section which only said fourth data is to be actually stored, and to control the selector means to select said data from the output means in a processing of a section in which only said data from the output means is to be actually stored.

Claim 9

A memory circuit formed on an LSI device, comprising: (a) memory means for effecting data read, data write and store data operations, and having input means, output means and a plurality of storage locations for storing data; and (b) control means having an output connected to said input means of said memory means, and including first data input means, second data input means, third data input means, fourth data input means, said second data input means being connected to receive data from said output means of said memory means, and logical operation means operating in a first mode to write data input from first data input means into said memory means in response to a first value of data received from said third data input means, and operating a second mode to transfer data received from said output means of said memory means via said second data input means to said memory means in inverted form in response to a combination of a first value of data input from said first data input means and a second value of data input from said third data input means and to transfer data received from said output means of said memory means via said second data input means to said memory means without modification in response to a combination of a second value of data input from said first data input means and a second value of data input from said third data input means.

Claim 10

A memory circuit formed on an LSI device, comprising: (a) memory means for effecting data read, data write and store data operations, and having input means, output means and a plurality of storage locations for storing data; and (b) control means having an output connected to said input means of said memory means, and including first data input means, second data input means, third data input means, fourth data input means, said second data input means being connected to receive data from said output means of said memory means, and logical operation means operating in a first mode to write data input from first data input means into said memory means in response to a first value of data received from said third data input means, and operating a second mode to transfer data received from said output means of said memory means via said second data input means to said memory means in inverted form in response to a combination of a first value of data input from said first data input means and a second value of data input from said third data input means and to transfer data received from said output means of said memory means via said second data input means to said memory means without modification in response to a combination of a second value of data input from said first data input means and a second value of data input from said third data input means.

Claim 11

A memory circuit according to claim 8, wherein said control means further includes arithmetic operation means operating in a third mode for summing the data from said first, second and third input means and for transferring the result of said summing to said memory means in response to a first value of data from said fourth input means.

Claim 12

A memory circuit according to claim 9, wherein said first and second modes are discriminated from each other by a control input signal applied to said third data input means from an external device.

Claim 13

A memory circuit according to claim 10, wherein said control input signal from an external device is a carry input signal.

Claim 14

A memory circuit according to claim 9, wherein said first data and said second data are added with a carry operation in said third mode by said arithmetic operation means.

Claim 15

A memory circuit according to claim 12, wherein a result of said addition with a carry operation effected on said second data is outputted to said memory means.

Claim 16

A memory circuit according to claim 9, further comprising: first and second selector means each for selecting a data item from a plurality of input data items, means for applying an output from said first selector means to said first data input means, means for applying an output from said second selector means to said third data input means as a control input signal from an external device, and means for independently controlling said first and second selector means.

Claim 17

A memory circuit according to claim 14, wherein input data to said first selector means in said second mode includes said data from an external device and an inverted data thereof, and input data to said second selector means includes 0 and 1.

Claim 18

A memory circuit according to claim 9, wherein said first, second and third modes of said control means each are specified by a plurality of control input signals from external devices applied to said third and fourth data input means.

Claim 19

A memory circuit according to claim 9, wherein said first, second and third modes of said control means each are specified by two control input signals from external devices applied to said third and fourth data input means.

Claim 20

A memory circuit according to claim 17, wherein said first, second and third modes are classified into two kinds of modes by one of said control input signals from external devices.

Claim 21

A memory circuit according to claim 18, wherein said two kinds of modes include an ordinary write mode or a logical operation mode and an arithmetic operation mode.

Claim 22

A memory circuit according to claim 19, wherein said ordinary write mode is discriminated from said logical operation mode by a control input signal different from said external control input signal specified to discriminate said two kinds of modes.

Claim 23

A memory circuit according to claim 18, wherein one of said control input signals from external devices in the arithmetic operation mode is a carry input signal.

Claim 24

A memory circuit according to claim 9, wherein said first data and said second data are subjected to an exclusive OR operation as a logic operation in said logic operation mode.

Claim 25

A memory circuit according to claim 9, wherein said first data and said second data are added with a carry operation in an operation in said arithmetic operation mode.

Claim 26

A memory circuit according to claim 23, wherein a carry result obtained from said arithmetic addition with a carry operation conducted in the arithmetic operation mode is outputted.

Claim 27

A memory circuit according to claim 16, further comprising: first and second selector means each for selecting a data item from a plurality of input data items, means for applying an output from said first selector means to said first data input means, means for applying an output from said second selector means to said third data input means as a control input signal from an external device, and means for independently controlling said first and second selector means.

Claim 28

A memory circuit according to claim 21, wherein said carry input signal is identical to the control signal for discriminating said ordinary write mode from said logic operation mode.

Claim 29

A memory circuit formed on an LSI device, comprising: (a) memory means for effecting data read, data write, and store data operations, and having input means, output means and a plurality of storage locations for storing data; and (d) control means having an output connected to said input means of said memory means, and including first data input means, second data input means, third data input means, fourth data input means, said second data input means being connected to receive data from said output means of said memory means, and arithmetic operation means for summing the data from said first, second and third input means and for transferring the result of said summing to said memory means in response to a first value of data from said fourth input means.

Claim 30

A memory circuit formed on an LSI device, comprising: (a) memory means for effecting data read, data write, and store data operations, and having input means, output means and a plurality of storage locations for storing data; and (d) control means having an output connected to said input means of said memory means, and including first data input means, second data input means, third data input means, fourth data input means, said second data input means being connected to receive data from said output means of said memory means, and arithmetic operation means for summing the data from said first, second and third input means and for transferring the result of said summing to said memory means in response to a first value of data from said fourth input means.