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Patent US4868621A successfully refreshed from Google Patents.
US4868621A
Expired / Lapsed
US
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Input protection circuit
Assignee: Toshiba Corp
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Filing: 1988-03-11
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Granted: 1989-09-19
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Expires: 2008-03-11
Abstract
Abstract An input protection circuit for prevention of electrostatic breakdown is provided. This circuit comprises, on a semiconductor substrate of a first conductivity type, a heavily doped region of a second conductivity type connected to an input terminal and a heavily doped region of the first conductivity type so that they are in contact with each other. This circuit may further include another heavily doped region of the second conductivity type connected to the ground level with it being opposite to the heavily doped region of the second conductivity type provided in the above-mentioned elementary circuit configuration. Thus, the p-n junction comprising heavily doped regions is formed to thereby lower the junction breakdown voltage when a breakdown due to an input of a high potential occurs, resulting in an increased electrostatic withstand voltage.
Inventors
- 👤 Junichi Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:57
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
82 words
An input protection circuit comprising: a heavily doped region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type, and connected to an input terminal; and a heavily doped region of the first conductivity type which is formed on said semiconductor substrate of the first conductivity type with it being in contact with said heavily doped region of the second conductivity type, and being surrounded by said heavily doped region of the second conductivity type.
Claim 2
Dependent Claim
82 words
An input protection circuit comprising: a heavily doped region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type, and connected to an input terminal; and a heavily doped region of the first conductivity type which is formed on said semiconductor substrate of the first conductivity type with it being in contact with said heavily doped region of the second conductivity type, and being surrounded by said heavily doped region of the second conductivity type.
Claim 3
Dependent Claim
40 words
A circuit as set forth in claim 1, wherein said heavily doped region of the second conductivity type is common to the drain of an output MOS transistor, thus providing a function to output a signal from said input terminal.
Claim 4
Dependent Claim
40 words
A circuit as set forth in claim 1, wherein said heavily doped region of the second conductivity type is common to the drain of an output MOS transistor, thus providing a function to output a signal from said input terminal.
Claim 5
Dependent Claim
129 words
An input protection circuit comprising: a first heavily doped region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type, and connected to an input terminal; a heavily doped region of the first conductivity type which is formed on said semiconductor substrate of the first conductivity type with it being in contact with said first heavily doped region of the second conductivity type, and being surrounded by said first heavily doped region of the second conductivity type; and a second heavily doped region of the second conductivity type which is formed on said semiconductor substrate of the first conductivity type with it being opposite to said first heavily doped region of the second conductivity type, and connected to a reference power source.
Claim 6
Dependent Claim
129 words
An input protection circuit comprising: a first heavily doped region of a second conductivity type which is formed on a semiconductor substrate of a first conductivity type, and connected to an input terminal; a heavily doped region of the first conductivity type which is formed on said semiconductor substrate of the first conductivity type with it being in contact with said first heavily doped region of the second conductivity type, and being surrounded by said first heavily doped region of the second conductivity type; and a second heavily doped region of the second conductivity type which is formed on said semiconductor substrate of the first conductivity type with it being opposite to said first heavily doped region of the second conductivity type, and connected to a reference power source.
Claim 7
Dependent Claim
42 words
A circuit as set forth in claim 4, wherein said heavily doped region of the first conductivity type is located between said first heavily doped region of the second conductivity type and said second heavily doped region of the second conductivity type.
Claim 8
Dependent Claim
40 words
A circuit as set forth in claim 4, wherein said heavily doped region of the second conductivity type is common to the drain of an output MOS transistor, thus providing a function to output a signal from said input terminal.
Claim 9
Dependent Claim
40 words
A circuit as set forth in claim 5, wherein said heavily doped region of the second conductivity type is common to the drain of an output MOS transistor, thus providing a function to output a signal from said input terminal.
References Cited (Backward Citations)
US4449158A
Cited
EP0057024A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |