US4868511A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital sequencing circuit
Assignee: Raytheon Co
•
Filing: 1988-02-22
•
Granted: 1989-09-19
•
Expires: 2008-02-22
Abstract
Abstract A digital sequencing apparatus produces a series of contiguous enable gates or strobe signals. The apparatus includes an even number, and at least two alternating stages of cross-coupling NOR gates alternating with cross-coupled NAND gates where one of the cross-coupled NOR gates in each stage has a merged AND gate at one input and one of the NAND gates in each stage has a cross-coupled OR gate at one input. This apparatus produces contiguous enable gates in response to complementary clock inputs to each of the stages upon the input of a start signal to the first two stages of the apparatus.
Inventors
- 👤 George S. Des Brisay. Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:13
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/1506; H03K5/15093
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
112 words
An apparatus comprising: an even number of, and at least two, alternating circuit stages connected to one another, where one of said two alternating stages comprises two cross-coupled NOR gates, with one of said NOR gates having an AND gate at one NOR gate input; and where the other of said two alternating stages comprises two cross-coupled NAND gates, with one of said NAND gates having an OR gate at one NAND gate input; wherein said apparatus produces a series of contiguous strobe signals in response to complementary clock signal inputs to each of said circuit stages when an initiating signal is input to first and second circuit stages in said apparatus.
Claim 2
Independent Claim
112 words
An apparatus comprising: an even number of, and at least two, alternating circuit stages connected to one another, where one of said two alternating stages comprises two cross-coupled NOR gates, with one of said NOR gates having an AND gate at one NOR gate input; and where the other of said two alternating stages comprises two cross-coupled NAND gates, with one of said NAND gates having an OR gate at one NAND gate input; wherein said apparatus produces a series of contiguous strobe signals in response to complementary clock signal inputs to each of said circuit stages when an initiating signal is input to first and second circuit stages in said apparatus.
Claim 3
Dependent Claim
29 words
The apparatus of claim 1 further comprising means for coupling the output of the last stage in said apparatus to the input of the first stage in said apparatus.
Claim 4
Dependent Claim
18 words
The apparatus of claim 1 wherein said cross-coupled NOR gates precede, and alternate with, said cross-coupled NAND gates.
Claim 5
Dependent Claim
23 words
The apparatus of claim 1 wherein said cross-coupled NAND gates precede, and alternate with, said cross-coupled NOR gates in stages in said apparatus.
Claim 6
Dependent Claim
17 words
The apparatus of claim 1 wherein said AND gate is merged with said one NOR gate input.
Claim 7
Dependent Claim
17 words
The apparatus of claim 1 wherein said OR gate is merged with said one NAND gate input.
Claim 8
Dependent Claim
29 words
The apparatus of claim 1 wherein said AND gate is merged with said one NOR gate input, and said OR gate is merged with said one NAND gate input.
Claim 9
Dependent Claim
296 words
A circuit comprising an even number of stages of alternating first and second types, wherein: said first type of stage comprises first and second NOR gates and an AND gate; a first input of said second NOR gate being connected to an output of said first NOR gate, an output of said second NOR gate being connected to a first input of said first NOR gate, and an output of said AND gate being connected to a second input of said first NOR gate; said second type of stage comprises first and second NAND gates and an OR gate; a first input of said second NAND gate being connected to an output of said first NAND gate, a first input of said first NAND gate being connected to an output of said OR gate, an output of said first NAND gate being connected to a first input of an AND gate of a succeeding stage of said circuit if there is one and otherwise to said first input of said AND gate of a first stage of said circuit, an output of said second NAND gate being connected to a second input of said first NAND gate; and wherein said circuit produces a series of contiguous strobe signals in response to a clock signal input to a second input of each said AND gate and a second input of each said OR gate, and a complementary clock signal input to a second input of each said NOR gate and a second input of each said NAND gate when an initiating SET signal is input to a third input of said first NOR gate in said first stage of said circuit and to a third input of said OR gate in a second stage of said circuit.
Claim 10
Dependent Claim
296 words
A circuit comprising an even number of stages of alternating first and second types, wherein: said first type of stage comprises first and second NOR gates and an AND gate; a first input of said second NOR gate being connected to an output of said first NOR gate, an output of said second NOR gate being connected to a first input of said first NOR gate, and an output of said AND gate being connected to a second input of said first NOR gate; said second type of stage comprises first and second NAND gates and an OR gate; a first input of said second NAND gate being connected to an output of said first NAND gate, a first input of said first NAND gate being connected to an output of said OR gate, an output of said first NAND gate being connected to a first input of an AND gate of a succeeding stage of said circuit if there is one and otherwise to said first input of said AND gate of a first stage of said circuit, an output of said second NAND gate being connected to a second input of said first NAND gate; and wherein said circuit produces a series of contiguous strobe signals in response to a clock signal input to a second input of each said AND gate and a second input of each said OR gate, and a complementary clock signal input to a second input of each said NOR gate and a second input of each said NAND gate when an initiating SET signal is input to a third input of said first NOR gate in said first stage of said circuit and to a third input of said OR gate in a second stage of said circuit.
Claim 11
Dependent Claim
24 words
The circuit of claim 8 wherein said AND gate of each of said first type of stage is merged with said first NOR gate.
Claim 12
Dependent Claim
24 words
The circuit of claim 8 wherein said OR gate of each of said second type of stage is merged with said first NAND gate.
Claim 13
Dependent Claim
43 words
The circuit of claim 8 wherein said AND gate of each of said first type of stage is merged with said first NOR gate and said OR gate of each of said second type of stage is merged with said first NAND gate.
Claim 14
Dependent Claim
295 words
A circuit comprising an even number of stages of alternating first and second types, wherein: said first type of stage comprises first and second NAND gates and an OR gate; a first input of said second NAND gate being connected to an output of said first NAND gate, an output of said second NAND gate being connected to a first input of said first NAND gate, and an output of said OR gate being connected to a second input of said first NAND gate; said second type of stage comprises first and second NOR gates and an AND gate; a first input of said second NOR gate being connected to an output of said first NOR gate, a first input of said first NOR gate being connected to an output of said AND gate, an output of said first NOR gate being connected to a first input of an OR gate of a succeeding stage of said circuit if there is one and otherwise to said first input of said OR gate of a first stage of said circuit, an output of said second NOR gate being connected to a second input of said first NOR gate; and wherein said circuit produces a series of contiguous strobe signals in response to a clock signal inputs to second input of each said OR gate and a second input of each said AND gate, and a complementary clock signal input to a second input of each said NAND gate and a second input of each said NOR gate when an initiating SET signal is input to a third input of said first NAND gate in said first stage of said circuit and to a third input of said AND gate in a second stage of said circuit.
Claim 15
Dependent Claim
295 words
A circuit comprising an even number of stages of alternating first and second types, wherein: said first type of stage comprises first and second NAND gates and an OR gate; a first input of said second NAND gate being connected to an output of said first NAND gate, an output of said second NAND gate being connected to a first input of said first NAND gate, and an output of said OR gate being connected to a second input of said first NAND gate; said second type of stage comprises first and second NOR gates and an AND gate; a first input of said second NOR gate being connected to an output of said first NOR gate, a first input of said first NOR gate being connected to an output of said AND gate, an output of said first NOR gate being connected to a first input of an OR gate of a succeeding stage of said circuit if there is one and otherwise to said first input of said OR gate of a first stage of said circuit, an output of said second NOR gate being connected to a second input of said first NOR gate; and wherein said circuit produces a series of contiguous strobe signals in response to a clock signal inputs to second input of each said OR gate and a second input of each said AND gate, and a complementary clock signal input to a second input of each said NAND gate and a second input of each said NOR gate when an initiating SET signal is input to a third input of said first NAND gate in said first stage of said circuit and to a third input of said AND gate in a second stage of said circuit.
Claim 16
Dependent Claim
24 words
The circuit of claim 12 wherein said OR gate of each of said first type of stage is merged with said first NAND gate.
Claim 17
Dependent Claim
24 words
The circuit of claim 12 wherein said AND gate of each of said second type of stage is merged with said first NOR gate.
Claim 18
Dependent Claim
43 words
The circuit of claim 12 wherein said OR gate of each of said first type of stage is merged with said first NAND gate and said AND gate of each of said second type of stage is merged with said first NOR gate.
References Cited (Backward Citations)
US3108227A
Cited
US3297950A
Cited
US3609569A
Cited
US3808544A
Cited
US4150305A
Cited
US4300060A
Cited
US4441198A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |