Error tolerant microprocessor

Claim 2

A microprocessor adapted for detecting and correcting soft errors occurring during program execution, the microprocessor comprising: (a) a plurality of multi-stage data serial shift registers, each said register storing in bit serial fashion data and instructions for the microprocessor, each said stage of said data shift registers having a corresponding stage in each of the other said data shift registers, the data stored in each set of corresponding stages of said data shift registers defining a multi-bit error correctable word; (b) a multi-stage multi-bit parallel shift register, each stage of said parallel shift register storing a multi-bit error code word, each said error correctable word having an associated error code word stored in said parallel shift register; (c) an error code generator responsive to error correctable words for generating, (i) an associated error code word for the error correctable word at the input of said data shift registers, and (ii) a check error code for the error correctable word at the output of said data shift registers; (d) an error cod comparator responsive to said error codes for generating an error signal when said error codes do not match; and (e) a data correction means responsive to said error signal for correcting said output error correctable word.

Claim 3

A microprocessor as defined in claim 1 wherein each said multi-stage data serial shift register contains equal number of stages and a recirculating control circuit for recirculating a bit and entering a new bit into the first stage of said shift register.

Claim 4

A microprocessor as defined in claim 1 wherein said parallel shift register comprises a plurality of bit serial shift registers, each said bit serial shift register containing equal number of stages.

Claim 5

A microprocessor as defined in claim 1 wherein said error code generator generates the associated error code word prior to its corresponding error correctable word entering into the input stages of said data serial shift registers and based on single error correction double error detection techniques.

Claim 6

A microprocessor capable of detecting and correcting errors occurring in its memory during program execution, the microprocessor comprising: (a) a plurality of multi-stage data serial shift registers and a plurality of multi-stage error code serial shift registers, each of said registers having the same number and sequence of stages, such that each stage has a corresponding stage in the sequence of each other register, said registers shifted in synchronism through their respective sequences; (b) an error code generator and comparator circuit operable to (i) generate and enter into the first stages of said error code shift registers a set of bits (error code), said error code being indicative of the corresponding set of bits (error correctable word) in the first stages of said data shift registers; (ii) generate a separate second error code in response to each error correctable word leaving the last stages of said data shift registers; (iii) compare each second error code with its respective first error code to detect any bit change in its corresponding error correctable word; and (d) a select decode circuit responsive to said error code generator and comparator to correct the bit change in the error correctable word leaving the last stages of said data serial shift registers.

Claim 7

A microprocessor capable of detecting and correcting errors occurring in its memory during program execution, the microprocessor comprising: (a) a plurality of multi-stage data serial shift registers and a plurality of multi-stage error code serial shift registers, each of said registers having the same number and sequence of stages, such that each stage has a corresponding stage in the sequence of each other register, said registers shifted in synchronism through their respective sequences; (b) an error code generator and comparator circuit operable to (i) generate and enter into the first stages of said error code shift registers a set of bits (error code), said error code being indicative of the corresponding set of bits (error correctable word) in the first stages of said data shift registers; (ii) generate a separate second error code in response to each error correctable word leaving the last stages of said data shift registers; (iii) compare each second error code with its respective first error code to detect any bit change in its corresponding error correctable word; and (d) a select decode circuit responsive to said error code generator and comparator to correct the bit change in the error correctable word leaving the last stages of said data serial shift registers.

Claim 8

A microprocessor as defined in claim 5 including a clock operable to synchronously shift bits from stage to stage in the serial shift registers.

Claim 9

A microprocessor as defined in claim 5 wherein said error code generator and comparator generates said error codes based on single error correction double error detection techniques.

Claim 10

A microprocessor as defined in claim 5 wherein said select decode circuit comprises a plurality of select decodes, each said select decode containing the address of a separate data shift register.

Claim 11

A microprocessor adapted for detecting and correcting soft errors occurring during program execution, the microprocessor comprising: (a) a bidirectional bus; (b) an arithmatic logic unit coupled to the bus for executing a program; (c) a control circuit coupled to the arithmatic unit and the bus for providing control instructions to the microprocessor responsive to said control circuit; (d) a memory for storing data and instructions during program execution, the memory comprising a plurality of multi-stage data serial shift registers, each said register storing in bit serial fashion data and instructions for the microprocessor, each said stage of said data shift registers having a corresponding stage in each of the other said data shift registers, the data stored in each set of corresponding stages of said data shift registers defining a multi-bit error correctable word; (e) a multi-stage multi-bit parallel shift register, each stage of said parallel shift register storing a multi-bit error code word, each said error correctable word having an associated error code word stored in said parallel shift register; (f) an error code generator responsive to error correctable words for generating, (i) an associated error code word for the error correctable word at the input of said data shift registers, and (ii) a check error code for the error correctable word at the output of said data shift registers; or responsive to said (g) an error code comparator error codes for generating an error signal when said error codes do not match; (h) a data correction means responsive to said error signal for correcting said output error correctable word.

Claim 12

A microprocessor adapted for detecting and correcting soft errors occurring during program execution, the microprocessor comprising: (a) a bidirectional bus; (b) an arithmatic logic unit coupled to the bus for executing a program; (c) a control circuit coupled to the arithmatic unit and the bus for providing control instructions to the microprocessor responsive to said control circuit; (d) a memory for storing data and instructions during program execution, the memory comprising a plurality of multi-stage data serial shift registers, each said register storing in bit serial fashion data and instructions for the microprocessor, each said stage of said data shift registers having a corresponding stage in each of the other said data shift registers, the data stored in each set of corresponding stages of said data shift registers defining a multi-bit error correctable word; (e) a multi-stage multi-bit parallel shift register, each stage of said parallel shift register storing a multi-bit error code word, each said error correctable word having an associated error code word stored in said parallel shift register; (f) an error code generator responsive to error correctable words for generating, (i) an associated error code word for the error correctable word at the input of said data shift registers, and (ii) a check error code for the error correctable word at the output of said data shift registers; or responsive to said (g) an error code comparator error codes for generating an error signal when said error codes do not match; (h) a data correction means responsive to said error signal for correcting said output error correctable word.

Claim 13

The microprocessor as defined in claim 9 wherein said control circuit is of a multi-level hierarchical architecture comprising the levels of: (a) a word control circuit to define bit level operations within a word cycle; (b) a function control circuit coupled to the word control circuit to implement complete functions and algorithms by providing sequential flow of instructions to said word control circuits; and (c) an instruction control circuit coupled to said function control circuit to initiate, monitor the sequence of functions and issue commands to said function control circuit.

Claim 14

The microprocessor as defined in claim 9 wherein said shift registers are recirculating type.

Claim 15

The microprocessor of claim 9 wherein each said serial shift register further comprises a recirculating control circuit for recirculating a bit and entering a new data bit into the first stage of said shift register.

Claim 16

The microprocessor as defined in claim 9 wherein said microprocessor comprises a single chip using a gallium arsenide substrate.

Claim 17

The microprocessor as defined in claim 9 said control circuit is a hierarchical type control circuit comprising multiple levels.

Claim 18

A microprocessor adapted for detecting and correcting soft errors occurring during program execution, the microprocessor comprising: (a) a bus; (b) an arithmatic logic unit for executing program instructions and for performing arithmatic and control functions; (c) a control circuit having a multi-level hierarchical structure, comprising the levels of: (i) a word control circuit to define bit level operations with a word cycle; (ii) a function control circuit coupled to the word control circuit to implement complete functions or algorithms by providing sequential flow of instructions to said word control circuits; and (iii) an instruction control circuit coupled to said function control circuit to initiate, monitor the sequence of functions and issue commands to said function control circuit; (d) a plurality of multi-stage data serial shift registers responsive to said control circuit for storing data and instructions during program execution and a plurality of multi-stage error code serial shift registers, both of said pluralities having the same number and sequence of stages, such that each stage in each register has a position in its sequence of stages corresponding to a separate stage in the sequence of each other register; (e) said two pluralities of registers operable to shift in synchronism bits in corresponding stages of the two pluralities of registers from a first stage to a last stage through their respective sequences of stages; (f) an error code generator and comparator circuit operable to (i) generate and enter into the first stages of said error code shift registers a set of bits (error code), said error code being indicative of the corresponding set of bits (error correctable word) in the first stages of said data shift registers; error code in (ii) generate a separate second response to each error correctable word leaving the last stages of said data shift registers; (iii) compare each second error code with its respective first error code to detect any bit change in its corresponding error correctable word; and (g) a select decode circuit responsive to said error code generator and comparator to correct the bit change in the error correctable word, the select decode circuit further comprising a plurality of select decodes, each said select decode being coupled to and containing an address of a corresponding data shift register.

Claim 19

A microprocessor adapted for detecting and correcting soft errors occurring during program execution, the microprocessor comprising: (a) a bus; (b) an arithmatic logic unit for executing program instructions and for performing arithmatic and control functions; (c) a control circuit having a multi-level hierarchical structure, comprising the levels of: (i) a word control circuit to define bit level operations with a word cycle; (ii) a function control circuit coupled to the word control circuit to implement complete functions or algorithms by providing sequential flow of instructions to said word control circuits; and (iii) an instruction control circuit coupled to said function control circuit to initiate, monitor the sequence of functions and issue commands to said function control circuit; (d) a plurality of multi-stage data serial shift registers responsive to said control circuit for storing data and instructions during program execution and a plurality of multi-stage error code serial shift registers, both of said pluralities having the same number and sequence of stages, such that each stage in each register has a position in its sequence of stages corresponding to a separate stage in the sequence of each other register; (e) said two pluralities of registers operable to shift in synchronism bits in corresponding stages of the two pluralities of registers from a first stage to a last stage through their respective sequences of stages; (f) an error code generator and comparator circuit operable to (i) generate and enter into the first stages of said error code shift registers a set of bits (error code), said error code being indicative of the corresponding set of bits (error correctable word) in the first stages of said data shift registers; error code in (ii) generate a separate second response to each error correctable word leaving the last stages of said data shift registers; (iii) compare each second error code with its respective first error code to detect any bit change in its corresponding error correctable word; and (g) a select decode circuit responsive to said error code generator and comparator to correct the bit change in the error correctable word, the select decode circuit further comprising a plurality of select decodes, each said select decode being coupled to and containing an address of a corresponding data shift register.

Claim 24

The method of claim 17 wherein said advancing step comprises: (a) entering bits into a first stage of each said shift register; and (b) shifting said bits through the stages of said shift registers.

Claim 25

The method of claim 17 wherein said generating a set of parallel error code bits is generated by using single error correction double error detection techniques.

Claim 26

The method of claim 17 wherein said synchronizing step is accomplished by a continuous clock.

Claim 27

A microprocessor adapted for detecting and correcting random errors occurring in its memory; the device comprising: (a) a means for synchronously advancing a parallel data bit set through said memory; (b) an error code generation means to generate two separate error codes corresponding to the parallel data bit set entering and leaving said memory; (c) an error code comparison means to compare said two error codes and to generate an error signal if there is not a match; and (d) a data correction means responsive to said error signal for correcting an error in said parallel data set leaving said memory.

Claim 28

A microprocessor adapted for detecting and correcting random errors occurring in its memory; the device comprising: (a) a means for synchronously advancing a parallel data bit set through said memory; (b) an error code generation means to generate two separate error codes corresponding to the parallel data bit set entering and leaving said memory; (c) an error code comparison means to compare said two error codes and to generate an error signal if there is not a match; and (d) a data correction means responsive to said error signal for correcting an error in said parallel data set leaving said memory.