Patent US4866494A successfully refreshed from Google Patents.
US4866494A
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US
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Semiconductor memory device having a plurality of memory cells of single transistor type
Assignee: NEC Corp
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Filing: 1987-10-07
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Granted: 1989-09-12
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Expires: 2007-10-07
Abstract
Abstract A new memory device of single transistor type is disclosed. A substrate has a surface portion of low impurity concentration and an inner portion of high impurity concentration, and a trench is formed in the substrate from the surface portion into the inner portion such that the trench surrounds a cell section of the substrate. A switching transistor is formed in the surface portion at the cell section, and a capacitor is formed in the trench such that a MOS type capacitor is constituted by a capacitor electrode, the lower side wall by the inner portion of the substrate and an insulating film therebetween. A bit line is connected to a conductive layer provided at the upper part of the trench, and the conductive layer is connected to the source or drain region of the transistor.
Inventors
- 👤 Susumu Kurosawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:36
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37; H10B12/373; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
369 words
A semiconductor memory device having a plurality of memory cells comprising a semiconductor substrate including a semiconductor body of one conductivity type and a semiconductor layer of one conductivity type having a lower impurity concentration than that of said semiconductor body and formed on said semiconductor body, a plurality of cell sections of said substrate, each of said cell sections having a rectangular shape in the plan view, a trench formed in said substrate from the surface of said semiconductor layer into said semiconductor body through said semiconductor layer and surrounding each of said cell sections such that said trench delineates said rectangular shape in the plan view of said cell section and that the side walls of said trench are constituted by lower side walls of said semiconductor body and upper side walls of said semiconductor layer, first insulating films formed on said lower side walls of said trench such that said first insulating film surround respective said rectangular shape cell sections, capacitor electrodes formed on said first insulating films, respectively, such that said capacitor electrodes surround respective said rectangular shape cell sections, each of said capacitor electrodes being provided above both of said lower and upper side walls at one side of said rectangular shape cell section and provided only above said lower side wall such that it is free from above said upper side wall at another side of said rectangular shape cell section, second insulating films provided on said capacitor electrodes, a common cell plate provided on said second insulating films such that said common cell plate is faced to respective said capacitor electrodes via said second insulating films, source and drain regions of the opposite conductivity type formed in said semiconductor layer of said cell sections, one of said source and drain regions being provided along said one sides of said cell sections and connected to said capacitor electrodes and the other of source and drain regions being provided along said another sides of said cell sections, conductive layers provided at the upper parts of said trench along said another sides of said cell sections and connected to said other of source and drain regions, and a bit line connected to said conductive layers.
Claim 2
Dependent Claim
369 words
A semiconductor memory device having a plurality of memory cells comprising a semiconductor substrate including a semiconductor body of one conductivity type and a semiconductor layer of one conductivity type having a lower impurity concentration than that of said semiconductor body and formed on said semiconductor body, a plurality of cell sections of said substrate, each of said cell sections having a rectangular shape in the plan view, a trench formed in said substrate from the surface of said semiconductor layer into said semiconductor body through said semiconductor layer and surrounding each of said cell sections such that said trench delineates said rectangular shape in the plan view of said cell section and that the side walls of said trench are constituted by lower side walls of said semiconductor body and upper side walls of said semiconductor layer, first insulating films formed on said lower side walls of said trench such that said first insulating film surround respective said rectangular shape cell sections, capacitor electrodes formed on said first insulating films, respectively, such that said capacitor electrodes surround respective said rectangular shape cell sections, each of said capacitor electrodes being provided above both of said lower and upper side walls at one side of said rectangular shape cell section and provided only above said lower side wall such that it is free from above said upper side wall at another side of said rectangular shape cell section, second insulating films provided on said capacitor electrodes, a common cell plate provided on said second insulating films such that said common cell plate is faced to respective said capacitor electrodes via said second insulating films, source and drain regions of the opposite conductivity type formed in said semiconductor layer of said cell sections, one of said source and drain regions being provided along said one sides of said cell sections and connected to said capacitor electrodes and the other of source and drain regions being provided along said another sides of said cell sections, conductive layers provided at the upper parts of said trench along said another sides of said cell sections and connected to said other of source and drain regions, and a bit line connected to said conductive layers.
Claim 3
Dependent Claim
43 words
A semiconductor memory device of claim 1, in which the impurity concentration of said semiconductor body is 1×10 18 atoms/cm 3 or more, and the impurity concentration of said semiconductor layer ranges from 5×10 17 atoms/cm 3 to 1×10 15 atoms/cm 3 .
Claim 4
Dependent Claim
22 words
A semiconductor memory device of claim 1, in which the thickness of said semiconductor layer ranges from 1 μm to 3 μm.
Claim 5
Dependent Claim
28 words
A semiconductor memory device of claim 1, in which said conductive layer is made of polycrystalline silicon having the same conductivity type as that of said impurity region.
Claim 6
Dependent Claim
339 words
A semiconductor memory device having a plurality of memory cells comprising a semiconductor substrate including a surface portion of one conductivity type and an inner portion of one conductivity type having a higher impurity concentration than that of said surface portion and provided under said surface portion, a plurality of cell sections of said substrate, a trench formed in said substrate from the surface of said surface portion into said inner portion through said surface portion and surrounding each of said cell sections such a that the side walls of said trench are constituted by lower side walls of said inner portion and upper side walls of said surface portion, first insulting films formed on said lower walls of said trench such that said first insulating films surround respective said cell sections, capacitor electrodes formed on said first insulating films, respectively, such that said capacitor electrodes surround respective said cell sections, each of said capacitor electrodes being provided only above said lower side wall such a that it is free from above said upper side wall except a part of said capacitor electrode for leading-out said capacitor electrode, second insulating films provided on said capacitor electrodes, a common cell plate provided on said second insulating films such that said common cell plate is faced to respective said capacitor electrodes via said second insulating films, transistors each including source and drain regions of the opposite conductivity type formed in said surface portion of said substrate, a channel region provided at said surface of said surface portion between said source and drain regions and a gate electrode formed on said channel region via a gate insulating film, one of said source and drain regions being connected to said part of said capacitor electrode, an insulating layer covering said trench and said transistors, a contact hole formed in said insulating layer above a part of said trench, and a bit line formed on said insulating layer and electrically coupled to the other of said source and drain regions through said contact hole.
Claim 7
Dependent Claim
339 words
A semiconductor memory device having a plurality of memory cells comprising a semiconductor substrate including a surface portion of one conductivity type and an inner portion of one conductivity type having a higher impurity concentration than that of said surface portion and provided under said surface portion, a plurality of cell sections of said substrate, a trench formed in said substrate from the surface of said surface portion into said inner portion through said surface portion and surrounding each of said cell sections such a that the side walls of said trench are constituted by lower side walls of said inner portion and upper side walls of said surface portion, first insulting films formed on said lower walls of said trench such that said first insulating films surround respective said cell sections, capacitor electrodes formed on said first insulating films, respectively, such that said capacitor electrodes surround respective said cell sections, each of said capacitor electrodes being provided only above said lower side wall such a that it is free from above said upper side wall except a part of said capacitor electrode for leading-out said capacitor electrode, second insulating films provided on said capacitor electrodes, a common cell plate provided on said second insulating films such that said common cell plate is faced to respective said capacitor electrodes via said second insulating films, transistors each including source and drain regions of the opposite conductivity type formed in said surface portion of said substrate, a channel region provided at said surface of said surface portion between said source and drain regions and a gate electrode formed on said channel region via a gate insulating film, one of said source and drain regions being connected to said part of said capacitor electrode, an insulating layer covering said trench and said transistors, a contact hole formed in said insulating layer above a part of said trench, and a bit line formed on said insulating layer and electrically coupled to the other of said source and drain regions through said contact hole.
References Cited (Backward Citations)
US4672410A
Cited
GB2184290A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-11 | 1993-03-13 | 1993-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-11 | 1997-03-13 | 1997-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-11 | 2001-03-13 | 2001-09-12 | $7700.00 | Window Closed / Lapsed |