Semiconductor memory device

Claim 1

A semiconductor memory device having source and drain regions formed on the surface of a semiconductor substrate, a floating gate for storing the electric charges formed on said semiconductor substrate through a first dielectric layer, a control gate for receiving a control signal for controlling the out-flow or in-flow of the electric charges stored in said floating gate formed on said floating gate through a second dielectric layer, and word lines and bit lines intersecting at memory cells of said memory device, comprising: a conductive diffusion region of impurities located beneath said floating gate and formed on the surface of said semiconductor substrate in a region different from said source and drain regions said conductive diffusion region forming a capacitance with said floating gate, said conductive diffusion region of impurities being electrically connected to said control gate, said control gate and diffusion region being elongated, said diffusion region and said control gate overlapping and having longitudinal axis parallel to each other in a region underlying said bit line, said diffusion region coupled to a number of memory cells which together form at least one-byte memory cells, a portion of said floating gate extending over said drain forming a tunnel-oxide area through said first dielectric layer, said control gate and one of said bit lines overlapping each other at said tunnel-oxide area.