Communications circuit having an interface for external address decoding

Claim 2

A controller circuit for controlling the receipt of input data by a data processing device, said input data containing an address field, comprising: input means for receiving said input data; an input register, connected to said input means, for storing the address field of said input data; an address register for storing a pre-assigned address value; a comparator, connected to said input register and to said address register, for comparing the contents of said input register to the contents of said address register; local data bus terminals; buffer control means, connected to said input means, for presenting said input data to said local data bus terminals for storage externally from said controller circuit, said buffer control means connected to said comparator so that said input data is retained responsive to the contents of said input register matching the contents of said address register; external address comparison interface terminals for connection to external address comparison logic; and interface logic, connected to said external address interface terminals and to said buffer control means, for disabling said buffer control means to retain said input data responsive to a match signal received upon said external address comparison interface terminals from said external address comparison logic.

Claim 3

The controller circuit of claim 1, wherein said input data is received serially by said input means.

Claim 4

The controller circuit of claim 1, wherein said buffer control means includes a memory address register, for storing a memory address to be presented on said local data bus terminals in conjunction with said input data; and wherein said buffer control means retains said input data by changing the contents of said memory address register.

Claim 5

The controller circuit of claim 1, wherein said external address comparison interface terminals comprise a first interface terminal for receiving a signal indicating a failed comparison, and a second interface terminal for receiving a signal indicating a matched comparison.

Claim 6

The controller circuit of claim 4, wherein said interface logic comprises: done signal means, connected to said first and second interface terminals, for generating a done signal responsive to receiving a signal on either of said first or second interface terminals; and result signal means, connected to said first and second interface terminals, for generating a result signal having a first logic state indicating that a signal was received on said first interface terminal, and having a second logic state indicating that a signal was received on said second interface terminal.

Claim 7

The controller circuit of claim 5, wherein said buffer control means further comprises: a receive data buffer for storing said input data; bus control means, for generating memory address information and for presenting the contents of said receive data buffer onto said local data bus terminals; buffer retention logic, comprising: internal comparison input means, connected to said comparator, for receiving the result of comparisons done by said comparator; external comparison input means for receiving said done signal and said result signal from said interface logic; and priority logic, connected to said internal and external comparison input means, for generating a retain signal responsive either to said comparator indicating that the contents of said input register match the contents of said address register, or to said result signal from said interface logic being in said second logic state in conjunction with said done signal; and buffer manager logic for modifying the contents of said memory address register responsive to said retain signal.

Claim 8

The controller circuit of claim 6, wherein said input data is received by said input means in formatted frames; wherein said memory address register stores the first address of a plurality of memory addresses generated by said bus control means for the storage of a frame of input data; and wherein said bus control means generates a memory address onto said local data bus terminals corresponding to the contents of said memory address register for the first word of a frame of input data to be stored.

Claim 9

An interface adapter for a communication network, comprising: a local data bus; a memory, connected to said local data bus, for temporary storage of data in addressable locations; a system interface, connected to said local data bus, for interface of said adapter to an external data processing device; input means for receiving input data from the communications network, said input data containing a first and a second address field; external address comparison logic, connected to said local data bus, for comparing said second address field in said input data to a second pre-assigned address value; and a controller circuit, connected to said input means and to said local data bus, comprising: an input register, connected to said input means, for storing said first address field of said input data; an address register for storing a first pre-assigned address value; a comparator, connected to said input register and to said address register, for comparing the contents of said input register to the contents of said address register; and buffer means, connected to said local data bus, for presenting data from said input data to said local data bus for storage in said memory; buffer control means, connected to said comparator and to said buffer means, for causing said buffer means to retain said data stored by said memory from said input data responsive to the contents of said input register matching the contents of said address register; and interface means, connected to said external address comparison logic, for controlling said buffer means to retain said data stored by said memory from said serial input data stream responsive to said second address field matching said second pre-assigned address value.

Claim 10

An interface adapter for a communication network, comprising: a local data bus; a memory, connected to said local data bus, for temporary storage of data in addressable locations; a system interface, connected to said local data bus, for interface of said adapter to an external data processing device; input means for receiving input data from the communications network, said input data containing a first and a second address field; external address comparison logic, connected to said local data bus, for comparing said second address field in said input data to a second pre-assigned address value; and a controller circuit, connected to said input means and to said local data bus, comprising: an input register, connected to said input means, for storing said first address field of said input data; an address register for storing a first pre-assigned address value; a comparator, connected to said input register and to said address register, for comparing the contents of said input register to the contents of said address register; and buffer means, connected to said local data bus, for presenting data from said input data to said local data bus for storage in said memory; buffer control means, connected to said comparator and to said buffer means, for causing said buffer means to retain said data stored by said memory from said input data responsive to the contents of said input register matching the contents of said address register; and interface means, connected to said external address comparison logic, for controlling said buffer means to retain said data stored by said memory from said serial input data stream responsive to said second address field matching said second pre-assigned address value.

Claim 11

The interface adapter of claim 8, wherein said input data is received serially by said input means.

Claim 12

The interface adapter of claim 8, wherein said buffer control means comprises: a memory address register, for storing the address in said memory in which said input data is to be temporarily stored; a receive data buffer for storing said input data; bus control means, for generating memory address information and for presenting the contents of said receive data buffer onto said local data bus; and buffer manager logic for modifying the contents of said memory address register responsive to said comparator determining that the contents of said input register match the contents of said address register, and responsive to said interface means determining that said second address field matches said second pre-assigned address value.

Claim 13

The interface adapter of claim 10, wherein said external address comparison logic comprises: means, connected to said local data bus, for comparing said second address field in said input data to said second pre-assigned address value; a fail terminal, connected to said comparing means, for presenting a signal corresponding to said second address field not matching said second pre-assigned address value to said interface means of said controller circuit; and a match terminal, connected to said comparing means, for presenting a signal corresponding to said second address field matching said second pre-assigned value to said interface means of said controller circuit.

Claim 14

The interface adapter of claim 11, wherein said interface means comprises: done signal means, connected to said fail and match terminals, for generating a done signal responsive to receiving a signal on either of said fail or match terminals; and result signal means, connected to said fail and match terminals, for generating a result signal having a first logic state indicating that a signal was received on said fail terminal, and having a second logic state indicating that a signal was received on said match terminal.

Claim 15

The interface adapter of claim 12, wherein said input data is received by said input means in formatted frames; and wherein said interface means of said controller circuit also comprises means, responsive to the receipt of the beginning of a frame by said input means, for generating a start-of-frame signal to said external address comparison logic via said fail and match terminals.