Microprocessor device with integrated auto-loaded timer

Claim 2

A microprocessor device formed in a single semiconductor body, comprising: a CPU including an ALU, a plurality of registers, input/output port means, an instruction register, a control ROM having an input coupled to the instruction register, internal CPU bus means interconnecting inputs and outputs of the ALU with said registers and said input/output port means, and interrupt means for the CPU, input/output terminals on said semiconductor body, a timer having a clock input, a latch register and a count register, the timer having an output coupled to said interrupt means of the CPU, and a control register for the timer, said count register being decremented by said clock input, and means for reloading said count register from said latch register when said counter register has decremented to zero, address/data bus means coupling said input/output port means of the CPU with said latch register and said control register of said timer, and with said input/output terminals.

Claim 3

A device according to claim 1 in combination with a read-only memory external to said semiconductor body and having address input and data output coupled to said input/output terminals.

Claim 4

A device according to claim 2 wherein instructions are coupled from said data output of said read-only memory via said input/output terminals, said address/data bus means, said input/output port means, and said internal CPU bus means to said instruction register of the CPU.

Claim 5

A device according to claim 3 wherein said address/data bus means is a single, bidirectional, multiplexed bus for transferring addresses and data.

Claim 6

A device according to claim 1 wherein said timer interrupts said CPU at fixed intervals.

Claim 7

A device according to claim 5 wherein said timer interrupts said CPU only when said control register has a given content.

Claim 8

A digital data communications system comprising: (a) a signal path, (b) a plurality of stations connected in said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: (i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; (ii) a single-chip microprocessor device containing a local CPU, local address/data bus means, a timer having a count register, a clocked decrement input for said count register, a latch register means for interrupting said local CPU when said count register decrements to zero, and means for loading said count register from said latch register when said count register decrements to zero, (iii) a local read/write memory coupled to said local bus means, (iv) coupling means connecting said system bus to said local bus means whereby said main CPU can access said local read/write memory and said local CPU can access said main memory, (v) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, (vi) transmit/receive control means responsive to receipt of data from said signal path in said receiving means to directly access said local read/write memory for writing received data to the local read/write memory and reading transmit data from the local read/write memory.

Claim 9

A digital data communications system comprising: (a) a signal path, (b) a plurality of stations connected in said signal path, each station receiving digital data from the path and transmitting digital data to said path, each said station comprising: (i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; (ii) a single-chip microprocessor device containing a local CPU, local address/data bus means, a timer having a count register, a clocked decrement input for said count register, a latch register means for interrupting said local CPU when said count register decrements to zero, and means for loading said count register from said latch register when said count register decrements to zero, (iii) a local read/write memory coupled to said local bus means, (iv) coupling means connecting said system bus to said local bus means whereby said main CPU can access said local read/write memory and said local CPU can access said main memory, (v) receiving means having an input coupled to said signal path and an output coupled to said local bus means, and transmitting means having an output coupled to said signal path and an input coupled to said local bus means, (vi) transmit/receive control means responsive to receipt of data from said signal path in said receiving means to directly access said local read/write memory for writing received data to the local read/write memory and reading transmit data from the local read/write memory.

Claim 10

A system according to claim 7 wherein said signal path is a closed, one-way path, and each station receives data from an upstream direction in the path and transmits data to a downstream direction in the path.

Claim 11

A system according to claim 8 wherein said access to said signal path is controlled by a token included in the transmitted data and passed from station to station around the closed path.

Claim 12

A system according to claim 9 wherein data is transmitted on said signal path in bit-serial format, said receiving means includes serial-to-parallel conversion means, said transmitting means includes parallel-to-serial conversion means, and wherein said local address/data bus means and said system bus are parallel busses.

Claim 13

A system according to claim 10 wherein a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred upon initiation by said main CPU via said system bus and said local bus means into said local read/write memory, and subsequently such frame is transferred under control of said transmit/receive control means via said local bus to said transmitting means.

Claim 14

A system according to claim 11 wherein said frames of data created in said main memory and transmitted on said signal path by said stations include a destination address identifying a particular one of the stations, and a source address identifying the originating station.

Claim 15

A system according to claim 7 wherein said local CPU executes instructions fetched from a local ROM via said local bus means, and said main CPU executes instructions fetched from said main memory via said system bus.

Claim 16

A system according to claim 13 wherein said timer interrupts execution of said instructions in said local CPU after a timer period determined by said count register.

Claim 17

A digital data communctions system comprising: (a) a closed, one-way, bit-serial signal path, (b) a plurality of independent stations connected in said signal path, each station receiving digital data including an access-control token from the path and transmitting digital data including an access-control token to said path, each said station comprising: (i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; (ii) a single-chip microprocessor device containing a local CPU, a timer having a count register a clocked decrement input to said count register a latch register, means to interrupt said local CPU when said count register decrements to zero, means to load the count register from the latch register when the count register decrements to zero, a control register for the timer, local address/data bus means interconnecting said local CPU and said latch register of the timer and said control register of the timer; (iii) a local read/write memory, (iv) first access control means connecting said system bus to said local bus means whereby said main CPU initiates direct access to said local read/write memory via said system bus and said local bus means, (iv) receiving means having a serial input coupled to said signal path and a parallel output coupled to said local address/data bus means, and transmitting means having a serial output coupled to said signal path and a parallel input coupled to said local address/data bus means, (v) second access means connecting said output of said transmitting means to said local bus means, to initiate access to said local read/write memory via said said local bus means for writing data received from the signal path to the local read/write memory and reading transmit data from the local read/write memory for coupling to the signal path.

Claim 18

A digital data communctions system comprising: (a) a closed, one-way, bit-serial signal path, (b) a plurality of independent stations connected in said signal path, each station receiving digital data including an access-control token from the path and transmitting digital data including an access-control token to said path, each said station comprising: (i) a main processor containing a main CPU, a main memory, and peripheral I/O devices, and having a system bus interconnecting said CPU, main memory, and peripheral I/O devices; (ii) a single-chip microprocessor device containing a local CPU, a timer having a count register a clocked decrement input to said count register a latch register, means to interrupt said local CPU when said count register decrements to zero, means to load the count register from the latch register when the count register decrements to zero, a control register for the timer, local address/data bus means interconnecting said local CPU and said latch register of the timer and said control register of the timer; (iii) a local read/write memory, (iv) first access control means connecting said system bus to said local bus means whereby said main CPU initiates direct access to said local read/write memory via said system bus and said local bus means, (iv) receiving means having a serial input coupled to said signal path and a parallel output coupled to said local address/data bus means, and transmitting means having a serial output coupled to said signal path and a parallel input coupled to said local address/data bus means, (v) second access means connecting said output of said transmitting means to said local bus means, to initiate access to said local read/write memory via said said local bus means for writing data received from the signal path to the local read/write memory and reading transmit data from the local read/write memory for coupling to the signal path.

Claim 19

A system according to claim 15 wherein said receiving means includes serial-to-parallel conversion means, said transmitting means includes parallel-to-serial conversion means, and wherein each of said local address/data bus means and said system bus includes a parallel bus.

Claim 20

A system according to claim 16 wherein a frame of a plurality of bytes of data to be transmitted is created in said main memory under control of said main CPU, and such frame is transferred upon initiation by said main CPU and control by said first access means via said system bus and said local bus means into said local read/write memory, and subsequently such frame is transferred under control of said second access means via said local bus means to said transmitting means.

Claim 21

A system according to claim 17 wherein said frame of data created in said main memory and transmitted on said signal path by said station includes a destination address identifying a particular one of the station which is to receive the data, and a source address identifying the originating station.

Claim 22

A system according to claim 15 wherein said local CPU executes instructions fetched from a local read-only memory external to said microprocessor device via said local bus means, and said main CPU executes instructions fetched from said main memory via said system bus.