Solid-state imaging system with an electronic auto-stop (iris) responsive to an output potential of imaging signal

Claim 2

A solid-state imaging system comprising: a plurality of photo-electric converting elements; first means for selectively accessing said elements; second means for selectivity accessing said elements, said second accessing means operating independently of said first accessing means; and means for automatically setting and varying the timing difference between said first and second accessing means with respect to accessing said photo-electric converting elements in accordance with the output level of the converted electrical signals.

Claim 3

A solid-state imaging system according to claim 1, wherein said plurality of photo-electric converting elements comprise a photo-diode MOS transistor type of picture element array and wherein said means for effecting control of the timing difference includes means for detecting and holding the peak value of said output level, corresponding to the white level thereof, and comprising the peak value with a reference white level and timing means for automatically controlling said timing difference.

Claim 4

A solid-state imaging system comprising: a plurality of photo-electric converting elements, each one converting light information into an electrical signal; an accessing circuit for reading-out the converted signal from selected photo-electric converting element; a reset circuit for resetting the photo-electric converting elements prior to accessing them; and a feed-back circuit for automatically controlling the time difference between the resetting and accessing of the photo-electric converting elements in response to the potential level of said converted signal and in accordance with a preset desired level.

Claim 5

A solid-state imaging system comprising: a plurality of photo-electric converting elements, each one converting light information into an electrical signal; an accessing circuit for reading-out the converted signal from selected photo-electric converting element; a reset circuit for resetting the photo-electric converting elements prior to accessing them; and a feed-back circuit for automatically controlling the time difference between the resetting and accessing of the photo-electric converting elements in response to the potential level of said converted signal and in accordance with a preset desired level.

Claim 6

A solid-state imaging system according to claim 3, wherein said feed-back circuit is comprised of first means for detecting and holding the peak value of said converted signal which is read-out, corresponding to the white level thereof, second means for comparing said peak value with a reference white level, and a sensitivity controlling circuit for automatically controlling aperture of a solid-state circuit image sensor associated with said plurality of photo-electric converting elements, said sensitivity controlling circuit is responsive to an output of said second means and to an input signal and a clock signal from a driver circuit which supplies said solid-state image sensor circuit with a clock signal used during accessing so as to generate an output signal for controlling the time difference between accessing and resetting of the photo-electric converting elements.

Claim 7

A solid-state imaging system according to claim 3, wherein said accessing circuit is comprised of a vertical shift register for timely outputting signals at output terminals thereat in response to corresponding timing signals, an interlace gate circuit responsive to odd and even frame field control signals coupled between the output terminals of said vertical shift register and respective control inputs of a driving circuit, said driving circuit providing accessing signals for reading-out said converted signal at an output line and which are respectively associated with photo-electric converting elements corresponding to individual odd or even vertical scanning lines in response to an associated high level control input signal in accordance with said interlace gate circuit receiving a corresponding output of said vertical shift register and a corresponding field control signal, and wherein said plurality of photo-electric converting elements are comprised of a photo-diode array including a plurality of rows of photo-diode picture elements each including a pair of series-connected MOSFETs, activated in response to associated horizontal and vertical scanning signals, and a photo-diode in series therewith and being connected between a corresponding horizontal signal line and reference ground, wherein said horizontal signal line is coupled to said output line in response to an access signal from said driving circuit.

Claim 8

A solid-state imaging system according to claim 5, further including a plurality of MOSFET switches for respectively coupling a horizontal signal line associated with a vertical scanning line with said output line providing converting signal read-out.

Claim 9

A solid-state imaging system according to claim 5, wherein said reset circuit is comprised of a sensitivity control means for effecting variable resetting control of selected rows of photo-diode picture elements and including a second vertical shift register for timely outputting signals at output terminals thereat in response to associated second timing signals, a second interlace gate circuit responsive to odd and even frame field control signals coupled between the output terminals of said second vertical shift register and control inputs of a second driving circuit, said driving circuit resetting individual rows of picture elements via a dummy resetting output line in accordance with the timing of a corresponding output of said second vertical shift register and a frame field control signal controlling said second interlace gate circuit as controlled by said feed-back circuit.

Claim 10

A solid-state imaging system according to claim 7, wherein said feed-back circuit is comprised of first means for detecting and holding the peak value of said converted signal which is read-out, corresponding to the white level thereof, second means for comparing said peak value with a reference white level, and a sensitivity controlling circuit responsive to an output of said second means and to the input and a clocking signal associated with said vertical register of said accessing circuit which controls the scanning timing of said photo-diode array and in accordance with the read timing of the imaging system generating a corresponding output for effecting automatic control of the white level.

Claim 11

A solid-state imaging system comprising: a plurality of photo-diode for accumulating electric charges in accordance with received light, a plurality of electronic switch elements respectively associated with each of said photo-diode for deriving therefrom the accumulated charges thereat that in response to an accessing signal output means coupled between said plurality of photo-diodes and an output line for deriving output signals representative of the amount of said charges in each of said photo-diodes being accessed; a reset circuit for resetting the accumulated charges in response to a reset signal prior to accessing them; a detection circuit responsive to serially-outputted signals and, a timing circuit for setting the timing difference of said reset signal from said accessing signal in response to the output of said detection circuit

Claim 12

A solid-state imaging system comprising: a plurality of photo-diode for accumulating electric charges in accordance with received light, a plurality of electronic switch elements respectively associated with each of said photo-diode for deriving therefrom the accumulated charges thereat that in response to an accessing signal output means coupled between said plurality of photo-diodes and an output line for deriving output signals representative of the amount of said charges in each of said photo-diodes being accessed; a reset circuit for resetting the accumulated charges in response to a reset signal prior to accessing them; a detection circuit responsive to serially-outputted signals and, a timing circuit for setting the timing difference of said reset signal from said accessing signal in response to the output of said detection circuit

Claim 13

A solid-state imaging system according to claim 9, wherein said detection circuit is comprised of a peak detector coupled to said output line for detecting and holding the peak value of an output signal, corresponding to the white level thereof, and a voltage comparator having a first input coupled to receive said peak value, a second input supplied with a reference value corresponding to a desired white level of an image being sensed by a solid-state image sensor circuit, comprised of said plurality of photo-diodes and an output coupled to said timing circuit.

Claim 14

A solid-state imaging system according to claim 10, wherein said timing circuit is responsive to the output of said voltage comparator and to an input signal and a clock signal from a driver circuit which supplies said solid-state image sensor circuit with a clock signal used during accessing so as to generate an output signal for controlling the time difference between accessing and resetting of the photo-electric converting elements.

Claim 15

A solid-state imaging system according to claim 11, wherein said plurality of photo-diodes are comprised of a photo-diodes are comprised of a photo-diode array including a plurality of rows of photo-diode picture elements associated with an image sensor circuit, each one including a pair of series-connected MOSFETs and a photo-diode in series therewith and connected between a corresponding horizontal signal line and reference ground, said series-connected MOSFETs are respectively activated in response to associated horizontal and vertical scanning signals, and wherein each horizontal signal line is coupled to said output line in response to an access signal from a scanning circuit via a MOSFET switch during read-out accessing.