Phase locked loop wherein phase comparing and filtering are performed by microprocessor

Claim 1

A phase-locked loop system in which a drive voltage is determined for a voltage-controlled oscillator to be synchronized to network clock signals, comprising: a voltage controlled oscillator means for creating at an output thereof internal clock signals; means for creating time interval clock signals from the network clock signals such that said time interval clock signals have a frequency which is lower than a frequency of the network clock signals; counter means connected to receive and count said internal clock signals; register means connected to the counter means for receiving a count therefrom and also connected to said time interval clock signals such that a current counter reading is transferred into the register means and stored at time points defined by said time interval clock signals; arithmetic means connected to receive the stored counter readings from the register means for defining an evaluation interval corresponding to a selectable plurality of said time interval clock signals, for defining a current counter reading for each evaluation interval, for forming a difference between a current evaluation interval counter reading and a counter reading corresponding to a preceding evaluation interval, for determining a phase deviation by comparing said difference to a rated value which is indicative of a drive voltage for said voltage controlled oscillator means at a nominal frequency of the oscillator means, and for summing up said phase deviations; filter means connected to receive the summed up deviations and for providing digital drive signals; digital-to-analog converter means for converting said digital drive signals to an analog drive voltage connected to control said voltage controlled oscillator means; and said counter means, register means, arithmetic means, filter means and digital-to-analog converter means forming a phase-locked loop to control said voltage-controlled oscillator means.