Patent US4863560A successfully refreshed from Google Patents.
US4863560A
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Fabrication of silicon structures by single side, multiple step etching process
Assignee: Xerox Corp
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Filing: 1988-08-22
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Granted: 1989-09-05
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Expires: 2008-08-22
Abstract
Abstract Three dimensional silicon structures are fabricated from (100) silicon wafers by a single side, multiple step ODE etching process. All etching masks are formed one on top of the other prior to the initiation of etching, with the coarsest mask formed last and used first. Once the coarse anisotropic etching is completed, the coarse mask is removed and the finer anisotropic etching is done. The preferred embodiment is described using a thermal ink jet channel plate as the three dimensional structure, where coarse etching step provides the reservoir and the fine etching step provides the ink channels.
Inventors
- 👤 William G. Hawkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:25
CPC Classifications
B; B81; B81C; B81C1/00; B81C1/00015; B81C1/00023; B81C1/00126; B41; B41J; B41J2/00; B41J2/005; B41J2/01; B41J2/135; B41J2/16; B41J2/1601; B41J2/1621; B41J2/1626; B41J2/1631; H; H10; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10P50/69; H10P50/691; H10P50/692; H10P50/693; H10P50/694; B81B; B81B2201/00; B81B2201/05; B81B2201/052; B81B2203/00; B81B2203/03; B81B2203/0323; B81B2203/0338; G; G02; G02B; G02B6/00; G02B6/24; G02B6/36; G02B6/3628; G02B6/3632; G02B6/3644; G02B6/3684; G02B6/3692
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
251 words
A method for fabricating a three dimensional structure from a silicon wafer whose surface is specifically oriented with respect to the (100) and (110) crystal planes of the wafer comprising the steps of: (a) forming a first layer of etch resistant material on both side surfaces of the wafer; (b) patterning the first layer of etch resistant material on one of the wafer surfaces to produce a plurality of precisely located vias therein for subsequent orientation dependent etching (ODE) of recesses, so that said recesses will be bounded by walls lying along the {111}planes of the wafer; (c) depositing a second layer of etch resistant material on both sides of the wafer and over the first layer of etch resistant material, including the via therein; (d) patterning the second layer of etch resistant material on the same side as patterned on the first layer of etch resistant material to produce at least one via within the boundary of one or each of the vias in said first layer of etch resistant material for production of relatively deep recesses in the wafer by ODE; (e) placing the wafer into an anisotropic etchant medium to produce relatively deep coarse recesses in the wafer through the vias in the second layer of etch resistant material; (f) removing the second layer of etch resistant material; and (g) replacing the wafer into the anisotropic etchant medium to produce relatively shallow, fine recesses in the wafer through the vias in the first layer of etch resistant material.
Claim 2
Independent Claim
251 words
A method for fabricating a three dimensional structure from a silicon wafer whose surface is specifically oriented with respect to the (100) and (110) crystal planes of the wafer comprising the steps of: (a) forming a first layer of etch resistant material on both side surfaces of the wafer; (b) patterning the first layer of etch resistant material on one of the wafer surfaces to produce a plurality of precisely located vias therein for subsequent orientation dependent etching (ODE) of recesses, so that said recesses will be bounded by walls lying along the {111}planes of the wafer; (c) depositing a second layer of etch resistant material on both sides of the wafer and over the first layer of etch resistant material, including the via therein; (d) patterning the second layer of etch resistant material on the same side as patterned on the first layer of etch resistant material to produce at least one via within the boundary of one or each of the vias in said first layer of etch resistant material for production of relatively deep recesses in the wafer by ODE; (e) placing the wafer into an anisotropic etchant medium to produce relatively deep coarse recesses in the wafer through the vias in the second layer of etch resistant material; (f) removing the second layer of etch resistant material; and (g) replacing the wafer into the anisotropic etchant medium to produce relatively shallow, fine recesses in the wafer through the vias in the first layer of etch resistant material.
Claim 3
Dependent Claim
11 words
The method of claim 1, wherein the wafer surface is (100).
Claim 4
Dependent Claim
34 words
The method of claim 1, wherein the wafer surface is at a precise angle with respect to (100) plane and toward (110) plane, so that anisotropic etching produces trapezoidal shaped recesses in the wafer.
Claim 5
Dependent Claim
37 words
The method of claim 1, wherein one or more additional etch resistance layers are added and patterned prior to step (e) with the coarsest patterned etch resistance material formed last to create a multi-layer sequential etching structure.
Claim 6
Dependent Claim
56 words
The method of claim 1, wherein the first layer of etch resistant material is a thermally grown oxide (SiO 2 ) having a thickness of about 5000Å, and wherein the second layer of etch resistant material is silicon nitride (Si 3 N 4 ) having a thickness sufficient to provide the desired robustness to the wafer.
Claim 7
Dependent Claim
77 words
The method of claim 5, wherein the three dimensional structure is a plurality of channel plates for assembly with a plurality of heater plates to produce a quantity of ink jet printheads, and wherein said vias in the silicon nitride is positioned within each of the vias in the thermal oxide, so that a predetermined border exists between the edges of the via in the silicon nitride and the edges of the vias in the thermal oxide.
Claim 8
Dependent Claim
44 words
The method of claim 6, wherein the vias in the thermal oxide each have a predetermined number of parallel extensions which will enable the production of ink channel recesses connected directly to an associated reservoir recess without the need for a separate process step.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-04 | 1993-03-06 | 1993-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-04 | 1997-03-06 | 1997-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-04 | 2001-03-06 | 2001-09-05 | $7700.00 | Window Closed / Lapsed |