Semiconductor memory device with redundant memory cell

Claim 2

A semiconductor memory device receiving an accessing address comprising: a plurality of memory cells; a decoder, connected to said memory cells, for selecting the memory cell corresponding to the accessing address; a redundant memory cell for replacing a faulty memory cell in the memory cells; a redundant decoder, connected to said redundant memory cell, for selecting the redundant memory cell; a first nonvolatile memory for storing an address of the faulty memory cell; a second nonvolatile memory for storing information indicating the use or nonuse of the redundant memory cell; a comparator means, connected to said first nonvolatile memory, said redundant decoder and said decoder, for comparing the accessing address with the address of the faulty memory cell stored in the first nonvolatile memory and for making the redundant decoder active and making the decoder inactive when the accessing address coincides with the address of the faulty memory cell; and a forced release circuit, connected to said comparator means and said second nonvolatile memory, for receiving a forced redundant release signal, for releasing the replacement of the faulty memory cell by the redundant memory cell, for making the decoder active, and for making the redundant decoder inactive by application of the forced redundant release signal to the comparator means, even when the accessing address coincides with the address of the faulty memory cell.

Claim 3

A semiconductor memory device as set forth in claim 1, wherein said forced release circuit receives the output of the comparator means and the output of said forced release circuit is applied to the decoder and the redundant decoder.

Claim 4

A semiconductor memory device as set forth in claim 2, wherein said forced release circuit is constituted by an inverter and a NOR gate and the output of the comparator means is applied to the input of the inverter, the output of the inverter is applied to one input of the NOR gate, the forced redundant release signal is applied to the other input of the NOR gate, and the output of the NOR gate is applied to the decoder and the redundant decoder.

Claim 5

A semiconductor memory device receiving an accessing address comprising: a plurality of memory cells; a decoder, connected to said memory cells, for selecting the memory cell corresponding to the accessing address; a redundant memory cell for replacing a faulty memory cell in the memory cells; a redundant decoder, connected to said redundant memory cell, for selecting the redundant memory cell; a first nonvolatile memory storing an address of the faulty memory cell; a second nonvolatile memory storing information indicating the use or nonuse of the redundant memory cell; a comparator means, connected to said first nonvolatile memory and connected to said second nonvolatile memory, for comparing the accessing address with the address of the faulty memory cell stored in the first nonvolatile memory and for making the redundant decoder active and making the decoder inactive when the accessing address coincides with the address of the faulty memory cell; and a forced release circuit, connected to said comparator means, said decoder and said redundant decode, said force release circuit for receiving a forced redundant release signal, for releasing the replacement of the faulty memory cell by the redundant memory cell, for making the decoder active, and for making the redundant decoder inactive by application of the forced redundant release signal, even when the accessing address coincides with the address of the faulty memory cell.

Claim 6

A semiconductor memory device receiving an accessing address comprising: a plurality of memory cells; a decoder, connected to said memory cells, for selecting the memory cell corresponding to the accessing address; a redundant memory cell for replacing a faulty memory cell in the memory cells; a redundant decoder, connected to said redundant memory cell, for selecting the redundant memory cell; a first nonvolatile memory storing an address of the faulty memory cell; a second nonvolatile memory storing information indicating the use or nonuse of the redundant memory cell; a comparator means, connected to said first nonvolatile memory and connected to said second nonvolatile memory, for comparing the accessing address with the address of the faulty memory cell stored in the first nonvolatile memory and for making the redundant decoder active and making the decoder inactive when the accessing address coincides with the address of the faulty memory cell; and a forced release circuit, connected to said comparator means, said decoder and said redundant decode, said force release circuit for receiving a forced redundant release signal, for releasing the replacement of the faulty memory cell by the redundant memory cell, for making the decoder active, and for making the redundant decoder inactive by application of the forced redundant release signal, even when the accessing address coincides with the address of the faulty memory cell.

Claim 7

A semiconductor memory device as set forth in claim 4, wherein said forced release circuit receives an output of the second nonvolatile memory and an output of said forced release circuit is applied to the comparator means.

Claim 8

A semiconductor memory device as set forth in claim 5, wherein said forced release circuit is constituted by an inverter and a NOR gate and the output of the second nonvolatile memory is applied to the input of the inverter, the output of the inverter is applied to one input of the NOR gate, the forced redundant release signal is applied to the other input of the NOR gate, and the output of the NOR gate is applied to the comparator means.

Claim 9

A semiconductor memory device as set forth in claim 1, 6, or 3, wherein said forced redundant release signal is obtained by applying a voltage different from a normal voltage to one terminal of a forced redundant release signal generating circuit of said semiconductor memory device.