Microcomputer having high-speed and low-speed operation modes for reading a memory

Claim 1

A microcomputer having a high-speed operation mode and a low-speed operation mode, comprising; a memory storing information used in said microcomputer, a reading circuit coupled to said memory for reading said information out of said memory, said reading circuit having an enable terminal and being activated by an operation-enable signal applied to said enable terminal, and a control circuit including means for producing a mode designating signal having a first level when said high-speed operation mode is designated and a second level when said low-speed operation mode is designated, means for intermittently producing a read control signal, means responsive to said first level mode designating signal for generating a first enable signal during the entire time period of said high-speed operation mode irrespective of said read control signal and for applying said first enable signal to said enable terminal of said reading circuit as said operation-enable signal, and means responsive to said second level mode designating signal and said read control signal for intermittently generating a second enable signal and for applying said second enable signal to said enable terminal of said reading circuit as said operation-enable signal, whereby said reading circuit is continuously activated during said high-speed operation mode by said first enable signal and is activated intermittently in said low-speed operation mode by said second enable signal.