Continuous-wave-modulation detectors using prediction methods

Claim 2

A detector for a first continuous-wave-modulation signal encoding an input signal, said detector developing an output signal that decodes said input signal for application to subsequent circuitry and comprising: means for applying said first continuous-wave-modulation signal to said detector; means for supplying a carrier signal; means for modulating said carrier signal with a predicted input signal to generate a second continuous-wave-modulation signal encoding said predicted input signal in substantially the same way said first continuous-wave-modulation signal encodes said input signal; means for comparing the instantaneous amplitudes of said first and second continuous-wave-modulation signals to generate a third continuous-wave-modulation signal, which encodes an error signal indicative of any difference between said input signal and said predicted input signal; means for decoding the error signal encoded in said third continuous-wave-modulation signal; means for combining said decoded error signal with said predicted input signal to develop an output signal; means for generating said predicted input signal based on previous said output signal; and means for supplying said output signal from said detector to said subsequent circuitry.

Claim 3

A detector as set forth in claim 1 wherein said continuous-wave-modulation is amplitude modulation, wherein said means for supplying a carrier signal includes a source of unmodulated carrier signal and wherein said means for modulating said carrier signal includes a first multiplier for multiplying said unmodulated carrier signal with said predicted input signal.

Claim 4

A detector as set forth in claim 2 where said means for decoding the error signal comprises: a synchronous detector synchronously detecting said third continuous-wave-modulation signal in accordance with said unmodulated carrier signal to generate a synchronous detection response; and means for supplying at least a fraction of said synchronous detection response to said means for combining as said decoded error signal.

Claim 5

A detector as set forth in claim 2 wherein said synchronous detector comprises: a second multiplier for multiplying said unmodulated carrier signal with said third continuous-wave-modulation signal to generate said synchronous detection response as their product.

Claim 6

A detector as set forth in claim 2 wherein said means for decoding the error signal comprises: a synchronous detector synchronously detecting a fraction of said third continuous-wave-modulation signal in accordance with said unmodulated carrier signal to generate said decoded error signal.

Claim 7

A detector as set forth in claim 5 wherein said synchronous detector comprises: a second multiplier for multiplying said unmodulated carrier signal with said fraction of said third continuous-wave-modulation signal to generate said synchronous detection response as their product.

Claim 8

A detector as set forth in claim 2 wherein said amplitude modulation has a suppressed carrier and said means for generating said predicted signal generates predicted signal equal to delayed output signal.

Claim 9

A detector as set forth in claim 2 wherein said means for generating said predicted signal generates predicted signal equal to delayed output signal as augmented by a constant.

Claim 10

A detector as set forth in claim 1 wherein said means for supplying a carrier signal is of a type that supplies first and second phases of unmodulated carrier signal in quadrature relationship with each other; wherein said means for modulating said carrier signal comprises a first multiplier for multiplying said first phase of unmodulated carrier signal with a first component portion of a predicted input signal to generate a first product signal, a second multiplier for multiplying said second phase of unmodulated carrier signal with a second component portion of a predicted input signal to generate a second product signal, and means for linearly combining said first and second product signals to generate said second continuous-wave-modulation signal, said first and second component portions of said predicted signal being mutually orthogonal; wherein said means for decoding the error signal comprises a first synchronous detector synchronously detecting at least a fraction of said third continuous-wave-modulation signal in accordance with said first phase of unmodulated carrier signal, thereby generating a first synchronous detection response, and a second synchronous detector synchronously detecting said at least a fraction of said third continuous-wave-modulation signal in accordance with said second phase of unmodulated carrier signal, thereby generating a second synchronous detection response; wherein said means for combining said decoded error signal with said predicted signal comprises means for combining at least a fraction of each of the first and second synchronous detection responses respectively with said first and said second component portions of said predicted input signal to develop first and second component portions respectively of said output signal; and wherein said means for generating said predicted input signal is of a type in which samples of the first and second component portions of said predicted input signal are formed from previous samples of the first and second component portions respectively of said output signal.

Claim 11

A detector as set forth in claim 9 where said first and second component portions of said predicted input signal are respectively real and imaginary portions thereof; wherein said first and second portions of said output signal are respectively real and imaginary portions thereof; and wherein said means for supplying a carrier signal comprises: a controlled oscillator having the frequency and phase of its output signals determined by a control signal; a third multiplier multiplying together the first and second portions of said output signal to generate a product signal; and means for low-pass filtering said product signal to generate said control signal.

Claim 12

A detector as set forth in claim 9 wherein said means for supplying a carrier signal comprises a beat-frequency oscillator and wherein means are included for vectorially adding the first and second portions of said output signal to generate to further output signal.

Claim 13

A detector as set forth in claim 9 for use with a first continuous-wave-modulation signal having a carrier component associated therewith, said detector including: means for combining said first and second portions of said output signal to generate a real portion of said output signal as multiplied by a factor; and means for combining said first and second portions of said output signal to generate a imaginary portion of said output signal as multiplied by a factor.

Claim 14

A detector as set forth in claim 12 wherein said means for supplying a carrier signal comprises: a controlled oscillator having the phase of its output signals determined by a control signal; means for differentially combining the first and second component portions of said output signal to generate a difference output signal; and means for low-pass filtering said difference output signal to generate said control signal.

Claim 15

A detector as set forth in claim 9 wherein said input signal includes in its real portion the entirety of an accompanying carrier signal; wherein said first and second component portions of said predicted input signal are respectively real and imaginary portions thereof; wherein said first and second portions of said output signal are respectively real and imaginary portions thereof; and wherein said means for supplying a carrier signal comprises: a controlled oscillator having the frequency a phase of its output signals determined by a control signal; and means for low-pass filtering the imaginary portion of said output signal to generate said control signal.

Claim 16

An analog adaptive synchronous demodulator for double sideband suppressed carrier amplitude modulated signals comprising: first multiplier means connected to receive a carrier signal and a detected output signal for generating a first product signal; subtractor means connected to receive a modulated suppressed carrier signal, said subtractor means being coupled to the output of said first multiplier means for subtracting said first product signal from said modulated suppressed carrier signal; second multiplier means connected to receive said carrier signal, said second multiplier means being coupled to the output of said subtractor means for generating a second product signal; and integrator means coupled to the output of said second multiplier means for generating said detector output signal, said detected output signal being fed back to said first multiplier means.

Claim 17

An analog adaptive synchronous demodulator for double sideband suppressed carrier amplitude modulated signals comprising: first multiplier means connected to receive a carrier signal and a detected output signal for generating a first product signal; subtractor means connected to receive a modulated suppressed carrier signal, said subtractor means being coupled to the output of said first multiplier means for subtracting said first product signal from said modulated suppressed carrier signal; second multiplier means connected to receive said carrier signal, said second multiplier means being coupled to the output of said subtractor means for generating a second product signal; and integrator means coupled to the output of said second multiplier means for generating said detector output signal, said detected output signal being fed back to said first multiplier means.

Claim 18

The demodulator according to claim 15 wherein said first and second multiplier means each comprises a four-quadrant analog multiplier, said subtractor means comprises a summing amplifier and said integrator means comprises an analog integrator.

Claim 19

The demodulator according to claim 16 wherein the gain of said first multiplier is equal to the ratio ##EQU13## where R 1 represents the value of resistance coupling the output of said first multiplier means to an input of said subtractor means; R 1 represents the value of resistance coupling the output of said first multiplier means to an input of said subtractor means; R 2 represents the value of resistance in the path taken to said subtractor means by said modulated suppressed carrier signal; and R 3 represents the value of resistance coupling said input of said subtractor means to a common ground.

Claim 20

The demodulator according to claim 16 wherein said subtractor means includes two inputs, one of said inputs being connected to receive said modulated suppressed carrier signal, the other of said inputs being coupled to the output of said first multiplier means and having biased at a predetermined voltage level above a common ground, and resistive means coupling the output of said subtractor means to said one of said inputs.

Claim 21

The demodulator according to claim 18 wherein said other of said inputs is biased at a predetermined voltage level above ground by a resistance coupled therebetween, the value of said resistance being equal to the value of said resistive means.

Claim 22

A technique for synchronous demodulation of double sideband suppressed carrier signals using an adaptive analog demodulation method, comprising the steps of: generating a first product signal by multiplying a carrier signal with a detected output signal; generating a difference signal by subtracting said first product signal from a demodulated suppressed carrier signal; generating a second product signal by multiplying said difference signal with said carrier signal; and integrating said second product signal to produce said detected output signal.

Claim 23

A technique for synchronous demodulation of double sideband suppressed carrier signals using an adaptive analog demodulation method, comprising the steps of: generating a first product signal by multiplying a carrier signal with a detected output signal; generating a difference signal by subtracting said first product signal from a demodulated suppressed carrier signal; generating a second product signal by multiplying said difference signal with said carrier signal; and integrating said second product signal to produce said detected output signal.

Claim 24

The technique of claim 20 including the step of filtering even harmonics of said modulated suppressed carrier signal.

Claim 25

A detector for amplitude-modulation signals, said detector comprising: means for supplying a first amplitude-modulation signal, which encodes an input signal; means for supplying an unmodulated carrier signal; means for amplitude-modulating said unmodulated carrier signal in accordance with a predicted input signal, thereby to generate a second amplitude-modulation signal; means for comparing the instantaneous amplitudes of said first and second amplitude-modulation signals to develop a suppressed-carrier third amplitude-modulation signal, which encodes an error signal; means for synchronously demodulating said third amplitude-modulation signal with said unmodulated carrier signal for decoding said error signal; means for combining said error signal with said predicted input signal to develop an output signal; and means for generating said predicted input signal based on a previous value of said output signal.

Claim 26

A detector for amplitude-modulation signals, said detector comprising: means for supplying a first amplitude-modulation signal, which encodes an input signal; means for supplying an unmodulated carrier signal; means for amplitude-modulating said unmodulated carrier signal in accordance with a predicted input signal, thereby to generate a second amplitude-modulation signal; means for comparing the instantaneous amplitudes of said first and second amplitude-modulation signals to develop a suppressed-carrier third amplitude-modulation signal, which encodes an error signal; means for synchronously demodulating said third amplitude-modulation signal with said unmodulated carrier signal for decoding said error signal; means for combining said error signal with said predicted input signal to develop an output signal; and means for generating said predicted input signal based on a previous value of said output signal.

Claim 27

A detector for amplitude-modulation signals as set forth in claim 22 wherein said first and second amplitude-modulation signals are at least partially suppressed-carrier in nature.

Claim 28

A detector for amplitude-modulation signals as set forth in claim 23 wherein said first and second amplitude-modulation signals have substantially completely suppressed carriers.

Claim 29

A detector for amplitude-modulation signals as set forth in claim 24 wherein said means for amplitude-modulating said unmodulated carrier comprises a first multiplier receptive of said predicted input signal and said unmodulated carrier signal, one as multiplier and the other as multiplicand, for generating said second amplitude-modulation signal as a product of said multiplier and multiplicand.

Claim 30

A detector for amplitude-modulation signals as set forth in claim 23 wherein said means for comparing said first and second amplitude-modulation signals comprises means for combining said first and second amplitude-modulation signals to develop said suppressed-carrier third amplitude-modulation signal.

Claim 31

A detector for amplitude-modulation signals as set forth in claim 26 wherein said means for decoding said error signal comprises a second multiplier receptive of said unmodulated carrier signal and said third amplitude-modulation signal, one as multiplier and the other as multiplicand, for generating said error signal as a product of said multiplier and multiplicand.

Claim 32

A detector for amplitude-modulation signals as set forth in claim 27 wherein said means for combining said error signal with said predicted input signal comprises an adder receiving said error signal and said predicted input signal as addends and summing said addends to develop said output signal.

Claim 33

A detector for amplitude-modulation signals as set forth in claim 28 wherein said means for generating said predicted input signal comprises a one sample period delay of said output signal.

Claim 34

A detector for amplitude-modulation signals as set forth in claim 23 wherein said first and second amplitude-modulation signals each have substantial carrier component.

Claim 35

A detector for amplitude-modulation signals as set forth in claim 30 wherein said means for amplitude-modulating said unmodulated carrier includes: a first adder for adding a pedestal value to said predicted input signal to generate a first sum signal; and a first multiplier receptive of said first sum signal and said unmodulated carrier signal, one as multiplier and the other as multiplicand, for generating said second amplitude-modulation signal as a product of said multiplier and multiplicand.

Claim 36

A detector for amplitude-modulation signals as set forth in claim 31 wherein said means for comparing said first and second amplitude-modulation signals comprises means for combining said first and second amplitude-modulation signals to develop said suppressed-carrier third amplitude-modulation signal.

Claim 37

A detector for amplitude-modulation signals as set forth in claim 32 wherein said means for decoding said error signal comprises a second multiplier receptive of said unmodulated carrier signal and said third amplitude-modulation signal, one as a multiplier and the other as multiplicand, for generating said error signal as a product of said multiplier and multiplicand.

Claim 38

A detector for amplitude-modulation signals as set forth in claim 33 wherein said means for combining said error signal with said predicted input signal comprises a second adder receiving said error signal and said predicted input signal as addends and summing said addends to develop said outpout signal.

Claim 39

A detector for amplitude-modulation signals as set forth in claim 34 wherein said means for generating said predicted input signal comprises a one sample period delay of said output signal.

Claim 40

A detector for amplitude-modulation signals, said detector comprising: means for supplying a first amplitude-modulation signal, which encodes an input signal; means for supplying an unmodulated carrier signal; means for amplitude-modulating said unmodulated carrier signal in response to an output signal, thereby to generate a second amplitude-modulation signal; means for comparing the instantaneous amplitudes of said first and second amplitude-modulation signals to develop a suppressed-carrier third amplitude-modulation signal, which encodes an error signal; means synchronously demodulating said third amplitude-modulation signal with said unmodulated carrier signal for decoding said error signal; means for combining said error signal with a predicted input signal to develop said output signal; and means for generating said predicted input signal by delaying said output signal.

Claim 41

A detector for amplitude-modulation signals, said detector comprising: means for supplying a first amplitude-modulation signal, which encodes an input signal; means for supplying an unmodulated carrier signal; means for amplitude-modulating said unmodulated carrier signal in response to an output signal, thereby to generate a second amplitude-modulation signal; means for comparing the instantaneous amplitudes of said first and second amplitude-modulation signals to develop a suppressed-carrier third amplitude-modulation signal, which encodes an error signal; means synchronously demodulating said third amplitude-modulation signal with said unmodulated carrier signal for decoding said error signal; means for combining said error signal with a predicted input signal to develop said output signal; and means for generating said predicted input signal by delaying said output signal.

Claim 42

A detector for amplitude-modulation signals as set forth in claim 36 wherein said first and second amplitude-modulation signals are at least partially suppressed-carrier in nature.

Claim 43

A detector for amplitude-modulation signals as set forth in claim 37 wherein said first and second amplitude-modulation signals have substantially completely suppressed carriers.

Claim 44

A detector for amplitude-modulation signals as set forth in claim 38 wherein said means for amplitude-modulating said unmodulated carrier comprises a first multiplier receptive of said output signal and said unmodulated carrier signal, one as multiplier and the other as multiplicand, for generating said second amplitude-modulation signal as a delayed product of said multiplier and multiplicand.

Claim 45

A detector for amplitude-modulation signals as set forth in claim 39 wherein said means for comparing said first and second amplitude-modulation signals comprises means for combining said first and second amplitude-modulation signals to develop said suppressed-carrier third amplitude-modulation signal.

Claim 46

A detector for amplitude-modulation signals as set forth in claim 40 wherein said means for decoding said error signal comprises a second multiplier receptive of delayed said unmodulated carrier signal and said third amplitude-modulation signal, one as multiplier and the other as multiplicand, for generating said error signal as a product of said multiplier and multiplicand.

Claim 47

A detector for amplitude-modulation signals as set forth in claim 41 wherein said means for combining said error signal with said predicted input signal comprises an adder receiving said error signal and said predicted input signal as addends and summing said addend to develop said output signal.

Claim 48

A detector for amplitude-modulation signals as set forth in claim 36 wherein said first and second amplitude-modulation signals both have substantial carrier components.

Claim 49

A detector for amplitude-modulation signals as set forth in claim 43 wherein said means for amplitude-modulating said unmodulated carrier includes: a first adder for adding a pedestal value to said output signal to generate a first sum signal; and a first multiplier receptive of said first sum signal and of said unmodulated carrier signal, one as multiplier and the other as multiplicand, for generating said second amplitude-modulation signal as a delayed product of said multiplier and multiplicand.

Claim 50

A detector for amplitude-modulation signals as set forth in claim 44 wherein said means for comparing said first and second amplitude-modulation signals comprises means for combining said first and second amplitude-modulations signals.

Claim 51

A detector for amplitude-modulation signals as set forth in claim 45 wherein said means for decoding said error signal consists of a second multiplier receptive of said third amplitude-modulation signal and of delayed said unmodulated carrier signal, one as multiplier and the other as multiplicand, for generating said error signal as a product of said multiplier and multiplicand.

Claim 52

A detector for amplitude-modulation signals as set forth in claim 46 wherein said means for combining said error signal with said predicted input signal comprises a second adder receiving said error signal and said predicted input signal as addends and summing said addends to develop said output signal.

Claim 53

A detector for incoming amplitude-modulation signals encoding an input signal, said detector including: a first input connection for receiving said amplitude-modulation signal encoding an input signal; a second input connection for receiving an unmodulated carrier signal; and an output connection for delivering an output signal, and being characterized by: an amplitude-modulator for modulating the unmodulated carrier signal in response to the output signal, thereby to provide a further amplitude-modulation signal; a linear combiner combining the incoming amplitude-modulation signal and the further amplitude-modulation signal to generate a suppressed-carrier amplitude-modulation signal encoding an error signal; a synchronous demodulator for decoding the error signal from the suppressed-carrier amplitude modulation signal with prescribed weight; a delay line providing a delayed response to the output signal; and an adder summing together the delayed response and the error signal with prescribed weight to generate the current value of the output signal applied to said output connection.

Claim 54

A detector for incoming amplitude-modulation signals encoding an input signal, said detector including: a first input connection for receiving said amplitude-modulation signal encoding an input signal; a second input connection for receiving an unmodulated carrier signal; and an output connection for delivering an output signal, and being characterized by: an amplitude-modulator for modulating the unmodulated carrier signal in response to the output signal, thereby to provide a further amplitude-modulation signal; a linear combiner combining the incoming amplitude-modulation signal and the further amplitude-modulation signal to generate a suppressed-carrier amplitude-modulation signal encoding an error signal; a synchronous demodulator for decoding the error signal from the suppressed-carrier amplitude modulation signal with prescribed weight; a delay line providing a delayed response to the output signal; and an adder summing together the delayed response and the error signal with prescribed weight to generate the current value of the output signal applied to said output connection.

Claim 55

A detector as set forth in claim 48 being characterized by said amplitude modulator modulating the unmodulated carrier signal in response to the output signal as delayed by said delay line.

Claim 56

A detector as set forth in claim 48 being characterized by said amplitude modulator modulating the unmodulated carrier signal in response to the output signal as applied thereto without appreciable delay from said output connection.