High speed, low drift sample and hold circuit

Claim 1

A sample and hold circuit having sample and hold modes, said circuit being for responding to an input signal exhibiting a voltage relative to a common potential and for providing an output signal, said circuit comprising: a first operation an amplifier having a signal input and an output; a second operational amplifier having a signal input and an output, the output from said second operational amplifier producing the output signal; a hold capacitor coupled between the signal input of said second operational amplifier and a ground terminal adapted to receive the common potential; a sample switch coupled between the output of said first operational amplifier and the signal input of said second operational amplifier, said sample switch including at least one of a predetermined type of switch and having an on-resistance being less than the on-resistance characteristic of two of the predetermined type of switches connected in series; an input terminal adapted to receive the input signal, said input terminal and the output of said second operational amplifier being coupled to the signal input of said first operational amplifier so that when the circuit is in the sample mode a signal produced at the output of said first operational amplifier corresponds to the input signal and when the circuit is in the hold mode the signal produced at the output of said first operational amplifier corresponds to the output signal and so that in the hold mode substantially no voltage difference appears across said sample switch.

Claim 14

A method of sampling and holding an input signal, the holding occurring during a hold mode, the sampling and holding being accomplished in a sample and hold circuit having a sample switch with input and output nodes and a hold capacitor coupled to the sample switch output node, said method comprising the steps of: buffering a voltage present on the hold capacitor to provide an output signal and reduce current drain on the hold capacitor; buffering an intermediate signal immediately before applying the intermediate signal to the sample switch input node to reduce resistance in series with the hold capacitor; and multiplexing between the input signal and the output signal to provide the intermediate signal so that when the sample and hold circuit is in the hold mode the input node of the sample switches experiences a voltage substantially equivalent to the voltage present on the hold capacitor.

Claim 15

A method of sampling and holding an input signal, the holding occurring during a hold mode, the sampling and holding being accomplished in a sample and hold circuit having a sample switch with input and output nodes and a hold capacitor coupled to the sample switch output node, said method comprising the steps of: buffering a voltage present on the hold capacitor to provide an output signal and reduce current drain on the hold capacitor; buffering an intermediate signal immediately before applying the intermediate signal to the sample switch input node to reduce resistance in series with the hold capacitor; and multiplexing between the input signal and the output signal to provide the intermediate signal so that when the sample and hold circuit is in the hold mode the input node of the sample switches experiences a voltage substantially equivalent to the voltage present on the hold capacitor.