US4860288A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Clock monitor for use with VLSI chips
Assignee: Control Data Corp
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Filing: 1987-10-23
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Granted: 1989-08-22
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Expires: 2007-10-23
Abstract
Abstract This application teaches that more accurate measurements of clock skew can be had by providing a clock monitor pin directly connected to the clock bus internal to the VLSI chip.
Inventors
- 👤 Judy L. Teske
- 👤 Brian D. Borchers
- 👤 Don A. Daane
- 👤 Daniel J. Baxter
- 👤 William G. Ehrich
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318552
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
66 words
For a chip having a system clock input pin with itnernally located system clock bus for distributing said clock input, a clock skew monitoring pin for providing an output at which the chip induced clock skew can be measured, said clock skew pin being in electrical connection with the system clock bus, said clock skew pin being a pin other than the system clock input pin.
Claim 2
Dependent Claim
66 words
For a chip having a system clock input pin with itnernally located system clock bus for distributing said clock input, a clock skew monitoring pin for providing an output at which the chip induced clock skew can be measured, said clock skew pin being in electrical connection with the system clock bus, said clock skew pin being a pin other than the system clock input pin.
Claim 3
Dependent Claim
75 words
For a chip having a system clock input pin with internally located system clock bus for distributing said clock input wherein said clock bus is located in the core logic area, a clock skew monitoring pin for providing an output at which the chip induced clock skew can be measured, said clock skew pin being in electrical connection with the system clock bus, said pin being a pin other than the system clock input pin.
Claim 4
Dependent Claim
75 words
For a chip having a system clock input pin with internally located system clock bus for distributing said clock input wherein said clock bus is located in the core logic area, a clock skew monitoring pin for providing an output at which the chip induced clock skew can be measured, said clock skew pin being in electrical connection with the system clock bus, said pin being a pin other than the system clock input pin.
Claim 5
Dependent Claim
36 words
In a VLSI circuit having a built-in on-chip test system having nearly all signal inputs and outputs going through a unit I/O cell having a means for monitoring clock skew as set forth in claim 1.
Claim 6
Independent Claim
117 words
A method for determining the clock skew caused by on-chip circuits associated with a clock input wherein said on-chip circuits are in a chip having an internally located system clock bus for distributing said clock input and means for monitoring clock skew comprising a clock skew measurement output pin in electrical connection with the system clock bus, said clock skew pin being a pin other than the one connected to receive the system clock input, said method comprising the steps of: (a) connecting the measurement means to said clock skew pin, (b) providing a clock signal as system clock input, and (c) measuring the skew induced in the clock by the chip at said clock skew pin.
Claim 7
Independent Claim
117 words
A method for determining the clock skew caused by on-chip circuits associated with a clock input wherein said on-chip circuits are in a chip having an internally located system clock bus for distributing said clock input and means for monitoring clock skew comprising a clock skew measurement output pin in electrical connection with the system clock bus, said clock skew pin being a pin other than the one connected to receive the system clock input, said method comprising the steps of: (a) connecting the measurement means to said clock skew pin, (b) providing a clock signal as system clock input, and (c) measuring the skew induced in the clock by the chip at said clock skew pin.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |