US4550405A
Expired / Lapsed
US
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Deskew circuit for automatic test equipment
Assignee: National Semiconductor Corp
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Filing: 1982-12-23
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Granted: 1985-10-29
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Expires: 2002-12-23
Abstract
Abstract An electrical pulse edge timing adjustment circuit 10 comprising one or more deskew elements 5. In each deskew element, a pulse train is passed through an inverter 20. The falling rate of pulse edges on the inverter output line 21 is controlled by a capacitor 24 and an adjustable current sink 25 which determine the output line capacitance discharge rate. From the output line, pulses are passed to another deskew element which re-inverts the pulses and delays the formerly rising pulse edges. Each current sink is independently adjustable to allow different delays in the rising and falling edges.
Inventors
- 👤 Burnell G. West
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:09
CPC Classifications
H; H10; H10P; H10P74/00; G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/13; H03K5/14; H10P74/27; H10P74/277
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
112 words
A circuit for delaying signals having voltage transitions comprising: an input node to which the signals are supplied; an intermediate output node; a reference potential source; interconnecting means coupled between the input node and the intermediate output node, the interconnecting means having a high output impedance for voltage transitions in a first direction, and a low output impedance for voltage transitions in an opposite direction; a capacitor connected between the reference potential source and the intermediate output node; and means, coupled to the capacitor, for discharging the capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction.
Claim 2
Dependent Claim
112 words
A circuit for delaying signals having voltage transitions comprising: an input node to which the signals are supplied; an intermediate output node; a reference potential source; interconnecting means coupled between the input node and the intermediate output node, the interconnecting means having a high output impedance for voltage transitions in a first direction, and a low output impedance for voltage transitions in an opposite direction; a capacitor connected between the reference potential source and the intermediate output node; and means, coupled to the capacitor, for discharging the capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction.
Claim 3
Dependent Claim
14 words
A circuit as in claim 1 wherein the interconnecting means comprises a logic gate.
Claim 4
Dependent Claim
16 words
A circuit as in claim 2 wherein the logic gate comprises an emitter coupled logic gate.
Claim 5
Dependent Claim
26 words
A circuit as in claim 3 wherein the logic gate inverts signals supplied to the input node before supplying those signals to the intermediate output node.
Claim 6
Dependent Claim
18 words
A circuit as in claim 1 wherein the means for discharging the capacitor comprises a controllable current sink.
Claim 7
Dependent Claim
19 words
A circuit as in claim 5 further comprising a resistor coupled between the capacitor and the intermediate output node.
Claim 8
Dependent Claim
19 words
A circuit as in claim 6 wherein the controllable current sink is connected between the resistor and the capacitor.
Claim 9
Dependent Claim
22 words
A circuit as in claim 1 wherein the interconnecting means comprises an inverter for inverting the signals supplied to the input node.
Claim 10
Dependent Claim
105 words
A circuit as in claim 8 further comprising: an output node; a second reference potential source; second interconnecting means coupled between the intermediate output node and the output node and having a high output impedance for voltage transitions in a first direction, and a low output impedance for voltage transitions in an opposite direction; a second capacitor connected between the output node and the second reference potential source; and second means, coupled to the second capacitor, for discharging the second capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction.
Claim 11
Dependent Claim
36 words
A circuit as in claim 9 wherein: the second means for discharging the second capacitor comprises a second controllable current sink; and wherein a second resistor is coupled between the second capacitor and the output node.
Claim 12
Dependent Claim
252 words
A circuit for delaying a pulse supplied at an input node comprising: an intermediate node; an output node; a first reference potential souce; a second reference potential source; first interconnecting means coupled between the input node and the intermediate node, the first interconnecting means having a high output impedance for voltage transitions in a first direction and a low output impedance for voltage transitions in an opposite direction; second interconnecting means for inverting signals supplied it coupled between the intermediate node and the output node, the second interconnecting means having a high output impedance for voltage transitions in a first direction, and a low output impedance for voltage transitions in an opposite direction; a first capacitor connected between the first reference potential source and the intermediate node; a second capacitor connected between the second reference potential source and the output node; a first resistor coupled between the intermediate node and the first capacitor; a second resistor coupled between the output node and the second capacitor; a first controllable current sink connected between the first capacitor and the first resistor for discharging the first capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction; and a second controllable current sink connected between the second capacitor and the second resistor, for discharging the second capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction.
Claim 13
Dependent Claim
252 words
A circuit for delaying a pulse supplied at an input node comprising: an intermediate node; an output node; a first reference potential souce; a second reference potential source; first interconnecting means coupled between the input node and the intermediate node, the first interconnecting means having a high output impedance for voltage transitions in a first direction and a low output impedance for voltage transitions in an opposite direction; second interconnecting means for inverting signals supplied it coupled between the intermediate node and the output node, the second interconnecting means having a high output impedance for voltage transitions in a first direction, and a low output impedance for voltage transitions in an opposite direction; a first capacitor connected between the first reference potential source and the intermediate node; a second capacitor connected between the second reference potential source and the output node; a first resistor coupled between the intermediate node and the first capacitor; a second resistor coupled between the output node and the second capacitor; a first controllable current sink connected between the first capacitor and the first resistor for discharging the first capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction; and a second controllable current sink connected between the second capacitor and the second resistor, for discharging the second capacitor at a controlled rate when voltage transitions are in the first direction and charging the capacitor when voltage transitions are in the opposite direction.
Claim 14
Dependent Claim
20 words
A circuit as in claim 11 wherein each of the first and second interconnecting means comprises an emitter coupled inverter.
Claim 15
Dependent Claim
22 words
A circuit as in claim 12 wherein each of the first and second reference potential sources comprises a source of ground potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-28 | 1989-04-29 | 1989-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-28 | 1993-04-29 | 1993-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-28 | 1997-04-29 | 1997-10-29 | $7700.00 | Window Closed / Lapsed |