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US4860235A
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Arithmetic unit with alternate mark inversion (AMI) coding
Assignee: Mitsubishi Electric Corp
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Filing: 1987-12-08
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Granted: 1989-08-22
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Expires: 2007-12-08
Abstract
Abstract An arithmetic unit having true and false deciding circuits (21 to 24) for receiving a first input signal A and a second input signal B to output the second input signal or complement of the same in response to the sign (most significant bit value) of the second input signal. The arithmetic unit further includes an adder (31 to 34) for receiving the first input signal A and output (M) from the true and false deciding circuits to output either A+M or A+M+1 in response to the sign (most significant bit value) of the second input signal B and an AND gate (50) for receiving the most significant bit F 4 of output F from the adder and the most significant bit value B 4 of the second input signal B. The arithmetic unit thus outputs the alternate mark inversion (AMI) code of the input signal B having the output of the AND gate (50) as a high order bit and the most significant bit F 4 of the output F of the adder as a low order bit, with a threshold value of the input signal A.
Inventors
- 👤 Harufusa Kondou
- 👤 Hideki Ando
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:00
CPC Classifications
H; H03; H03M; H03M5/00; H03M5/02; H03M5/16; H03M5/18; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4923; H04L25/4925
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
175 words
An arithmetic unit for receiving a first input signal of a plurality of bits and a second input signal of a plurality of bits to perform one of a plurality of operations designated by function selecting signals with respect to said first and second input signals, said arithmetic unit comprising: means for generating first, second and third control signals being in combination of prescribed values in response to a bit value indicating the sign of said second input signal and said function selecting signals; means for selectively outputting either said second input signal or complement of said second input signal in response to said first and second control signals; means for adding up said first input signal, output of said selective output means and said third control signal; and means for receiving said bit indicating said sign of said second input signal and the most significant bit of output of said addition means to output the alternate mark inversion (AMI) code of said second input signal with a threshold value of said first input signal.
Claim 2
Dependent Claim
175 words
An arithmetic unit for receiving a first input signal of a plurality of bits and a second input signal of a plurality of bits to perform one of a plurality of operations designated by function selecting signals with respect to said first and second input signals, said arithmetic unit comprising: means for generating first, second and third control signals being in combination of prescribed values in response to a bit value indicating the sign of said second input signal and said function selecting signals; means for selectively outputting either said second input signal or complement of said second input signal in response to said first and second control signals; means for adding up said first input signal, output of said selective output means and said third control signal; and means for receiving said bit indicating said sign of said second input signal and the most significant bit of output of said addition means to output the alternate mark inversion (AMI) code of said second input signal with a threshold value of said first input signal.
Claim 3
Dependent Claim
41 words
An arithmetic unit in accordance with claim 1, wherein said first input signal is a binary number indicating a positive value and said second input signal and said output of said addition means are binary numbers expressed in two's complement form.
Claim 4
Dependent Claim
43 words
An arithmetic unit in accordance with claim 1, wherein said selective passing means passes the complement of said second input signal when said second input signal is positive or 0 while outputting said second input signal when said second input signal is negative.
Claim 5
Dependent Claim
34 words
An arithmetic unit in accordance with claim 1, wherein said third control signal is "1" when said second input signal is positive or 0 while being "0" when said second input signal is negative.
Claim 6
Dependent Claim
47 words
An arithmetic unit in accordance with claim 4, wherein said AMI code is provided by a two-bit binary number having the most significant bit of said output of said addition means as a low order bit and output of said AND means as a high order bit.
Claim 7
Dependent Claim
39 words
An arithmetic unit in accordance with claim 1, wherein said AMI coding means includes AND means for receiving the most significant bit of said output of said addition means and the most significant bit of said second input signal.
Claim 8
Dependent Claim
42 words
An arithmetic unit in accordance with claim 1, wherein said addition means is formed by a plurality of full adders so that said third control signal is supplied to carry input of a full adder for addition of the least significant bit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |