Patent US4860202A successfully refreshed from Google Patents.
US4860202A
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US
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IR decoder system
Assignee: Zenith Electronics LLC
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Filing: 1984-07-05
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Granted: 1989-08-22
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Expires: 2004-07-05
Abstract
Abstract A microprocessor based infrared (IR) decoding system operating with binary data including data bits preceded by synchronizing bits has an input flip flop for triggering a counter responsive to a synchronizing bit and activating a latch type flip flop a predetermined time later for interrogating the data and storing the data bit. The counter also operates another flip flop which signals the microprocessor that a data bit is in the latch. The microprocessor is thus able to process the data in the latch in a time interval ending just before occurrence of the next data bit. The counter triggers the input flip flop to reset and rearm the counter before the next synchronizing bit.
Inventors
- 👤 Gary A. Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:22
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
85 words
A microprocessor decoding system including a microprocessor comprising: means for receiving binary data in the form of a synchronizing bit followed a predetermined time later by a data bit; latch means, coupled to said receiving means, responsive to said synchronizing bit for temporarily storing said data bit; and means responsive to said latch means for signalling said microprocessor that a data bit is being temporarily stored to enable processing of said stored data bit by said microprocessor prior to occurrence of the next data bit.
Claim 2
Dependent Claim
85 words
A microprocessor decoding system including a microprocessor comprising: means for receiving binary data in the form of a synchronizing bit followed a predetermined time later by a data bit; latch means, coupled to said receiving means, responsive to said synchronizing bit for temporarily storing said data bit; and means responsive to said latch means for signalling said microprocessor that a data bit is being temporarily stored to enable processing of said stored data bit by said microprocessor prior to occurrence of the next data bit.
Claim 3
Dependent Claim
23 words
The system of claim 1 wherein said latch means sample said binary data after said predetermined time when said data bit is present.
Claim 4
Dependent Claim
21 words
The system of claim 2 wherein said binary data is sampled immediately subsequent to the leading edge of said data bit.
Claim 5
Dependent Claim
35 words
The system of claim 3 wherein said latch means include a counter, and a latch supplied with said binary data, said counter activating said latch to sample said binary data and store said data bit.
Claim 6
Dependent Claim
48 words
The system of claim 4 wherein said counter is driven from said microprocessor and wherein said receiving means comprise an RS flip flop coupled to said counter and receiving said binary data, said counter resetting said RS flip flop just prior to occurrence of a subsequent synchronizing bit.
Claim 7
Dependent Claim
118 words
A microprocessor based decoding system for processing binary data in the form of synchronizing bits followed a predetermined time by data bits comprising: a counter in time synchronism with said microprocessor; a flip flop coupled to said counter and receiving said binary data for actuating said counter responsive to a synchronizing bit in said binary data; a latch receiving said binary data and being energized by said counter after said predetermined time during occurrence of a data bit for temporarily storing said data bit; means responsive to said counter for signalling said microprocessor when said data bit is stored; and said counter resetting said flip flop to reset said counter prior to occurrences of the next synchronizing bit.
Claim 8
Dependent Claim
118 words
A microprocessor based decoding system for processing binary data in the form of synchronizing bits followed a predetermined time by data bits comprising: a counter in time synchronism with said microprocessor; a flip flop coupled to said counter and receiving said binary data for actuating said counter responsive to a synchronizing bit in said binary data; a latch receiving said binary data and being energized by said counter after said predetermined time during occurrence of a data bit for temporarily storing said data bit; means responsive to said counter for signalling said microprocessor when said data bit is stored; and said counter resetting said flip flop to reset said counter prior to occurrences of the next synchronizing bit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |