Integrated analog-to-digital converter

Claim 2

A feedback coder comprising summation means having first and second inputs and an output, said first input of said summation means receiving an analog signal to be coded, first filter means having an input operably connected to said output of said summation means, analog-to-digital conversion means having an input operably connected to said first filter means and an output, second filter means operably connected between said output of said analog-to-digital conversion means and said second input of said summation means, digital-to-analog conversion means operably connected between said output of said analog-to-digital conversion means and said second filter means, the output of said analog-to-digital conversion means forming the coder output, each of said filter means comprising CMOS push/pull amplification means.

Claim 3

The coder of claim 1, further comprising adaptive step size means operably connected to said digital-to-analog conversion means.

Claim 4

The coder of claim 1, wherein said analog-to-digital conversion means comprises comparator means and latch means.

Claim 5

The coder of claim 1, wherein said analog-to-digital conversion means comprises a bistable circuit.

Claim 6

The coder of claim 4, wherein said bistable circuit is a D-type flip-flop circuit.

Claim 7

The coder of claim 1, wherein said digital-to-analog conversion means comprises switch means.

Claim 8

A feedback coder comprising first and second summation means, each having first and second inputs and an output, said first input of said first summation means receiving an analog signal to be coded, first filter means operably connected between said output of said first summation means and said first input of said second summation means, second filter means, analog-to-digital conversion means, and digital-to-analog conversion means, said second filter means being operably connected between said output of said second summation means and said analog-to-digital conversion means, said analog-to-digital conversion means being operably connected between said second filter means and the input of said digital-to-analog conversion means, the output of said digital-to-analog conversion means being connected to said second input of each of said first and second summation means, the output of said analog-to-digital conversion means forming the coder output, each of said first and second filter means comprising CMOS push/pull amplification means.

Claim 9

A feedback coder comprising first and second summation means, each having first and second inputs and an output, said first input of said first summation means receiving an analog signal to be coded, first filter means operably connected between said output of said first summation means and said first input of said second summation means, second filter means, analog-to-digital conversion means, and digital-to-analog conversion means, said second filter means being operably connected between said output of said second summation means and said analog-to-digital conversion means, said analog-to-digital conversion means being operably connected between said second filter means and the input of said digital-to-analog conversion means, the output of said digital-to-analog conversion means being connected to said second input of each of said first and second summation means, the output of said analog-to-digital conversion means forming the coder output, each of said first and second filter means comprising CMOS push/pull amplification means.

Claim 10

The coder of claim 7, further comprising signal polarity inverting means operably connected between said digital-to-analog conversion means and said second summation means.

Claim 11

The coder of claim 7, wherein said first and second filter means each comprise first order low pass filters.

Claim 12

The coder of claim 7, wherein said first and second filter means each comprises single order integrators.

Claim 13

The coder of claim 7, wherein said analog-to-digital conversion means comprises comparator means and latch means.

Claim 14

The coder of claim 7, wherein said analog-to-digital conversion means comprises a bistable circuit.

Claim 15

The coder of claim 12, wherein said bistable circuit is a D-type flip-flop circuit.

Claim 16

A feedback coder comprising first and second summation means, each having first and second inputs and an output, first and second filter means, and bistable means, said first input of said first summation means being operably connected to receive the analog input to be coded, the input of said first filter means being operably connected to the output of said first summation means, said first input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said output of said bistable means being operably connected to said second input of said second summation means, said second input of said first summation means and the coder output, each of said filter means comprising CMOS push/pull amplification means.

Claim 17

A feedback coder comprising first and second summation means, each having first and second inputs and an output, first and second filter means, and bistable means, said first input of said first summation means being operably connected to receive the analog input to be coded, the input of said first filter means being operably connected to the output of said first summation means, said first input of said second summation means being operably connected to the output of said first filter means, the input of said second filter means being operably connected to the output of said second summation means, the input of said bistable means being operably connected to the output of said second filter means, said output of said bistable means being operably connected to said second input of said second summation means, said second input of said first summation means and the coder output, each of said filter means comprising CMOS push/pull amplification means.

Claim 18

The coder of claim 14, further comprising first inverter means operably connected between said output of said bistable means and said second input of said first summation means.

Claim 19

The coder of claim 15, further comprising second inverter means operably connected between said first inverter means and said coder output.

Claim 20

The coder of claim 16, further comprising third inverter means operably connected between said output of said bistable means and said second input of said second summation means.

Claim 21

The coder of claim 14, wherein said bistable means comprises a D-type flip-flop circuit.

Claim 22

The coder of any of claims 1, 7 or 14 for use with a decimator comprising finite impulse response filter means and sub-sampling means.

Claim 23

The coder of claim 19, wherein said finite impulse response filter means and subsampler means comprise partial coefficient generator means and accumulator means.

Claim 24

The coder of claim 20, wherein said partial coefficient generator means comprises memory means having address means and data output means, counter means and shift register means, the output of said coder, the output of said counter means, and the output of said shift register means being operably connected to said address means and said data output means being operably connected to said accumulator means.

Claim 25

The coder of claim 21, wherein said memory means is a read only memory.

Claim 26

The coder of claim 21, wherein said counter means comprises a multi-bit counter.

Claim 27

The coder of claim 21, wherein said shift register means comprises series connected shift registers, each having an output operably connected to said address means.

Claim 28

The coder of claim 20, further comprising means for generating a plurality of ordered timing pulse trains, each pulse train having a frequency which is a given fraction of the frequency of the prior timing signal in order and wherein said partial coefficient generator means comprises means for receiving said coder output, means for delaying said coder output, a plurality of selector logic means, each of said logic means receiving a different one of said pulse trains, said coder output and said delayed coder output and generating one bit of a parallel output word.

Claim 29

The coder of claim 25, wherein each of said logic means comprises means for forming an output to be at the same state as the state of the received pulse train, if the coder output is in a high state, to be the complement of the state of the received pulse train, if the delayed coder output is in a high state, to be a high state if both the coder output and the delayed coder output are in the high state, and to be a low state if both the coder output and the delayed coder output are in the low state.

Claim 30

The coder of claim 20, wherein said generator generates a parallel output word and wherein said accumulator means comprises means for delaying each bit of said output word by an interval which is a function of the position of the bit in said output word.

Claim 31

The coder of claim 27, wherein said accumulator comprises a plurality of stages and wherein the output of said delaying means is applied to the input of the first stage at the word rate of said coder output.

Claim 32

The coder of claim 28, wherein each of said stages comprises adder means having first and second data inputs, a clock input, a sum output and a carry output, said first data input of each of said adder means receiving a different bit from the output of said delaying means, means for operably connecting said second data input of each adder means with said sum output thereof and means for operably connecting said clock input to said carry output of the adder means of said preceding stage.

Claim 33

The coder of claim 29, wherein said means for connecting said second data input of each adder means to said sum output thereof comprises sum output delay means.

Claim 34

The coder of claim 29, wherein said means for connecting said clock input of each adder means to said carry output of said adder means of said preceding stage comprises carry output delay means.

Claim 35

The coder of claim 29, wherein said accumulator further comprises a multiplexer comprising said given number of shift register stages respectively corresponding with said stages, and connected in tandem, each of said shift register stages having an output, each of said outputs being operably connected to said sum output delay means of the corresponding stage.

Claim 36

The coder of claim 32, wherein said multiplexer further comprises means for inverting the output of the last shift register stage.