Patent US4859928A successfully refreshed from Google Patents.
US4859928A
Expired / Lapsed
US
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CMOS comparator bias voltage generator
Assignee: Tektronix Inc
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Filing: 1988-12-20
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Granted: 1989-08-22
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Expires: 2008-12-20
Abstract
Abstract An apparatus for generating a CMOS comparator bias voltage for a CMOS comparator includes a dummy comparator having a negative input and a positive input coupled together to receive a common mode reference voltage corresponding to the common mode input voltage of the CMOS comparator. The dummy comparator also includes a bias input and an output. The apparatus for generating a CMOS comparator bias voltage further includes a bias amplifier having a negative input coupled to the output of the dummy comparator, a positive input for receiving a threshold reference voltage corresponding to the input threshold of the next stage driven by the CMOS comparator, and an output coupled to the bias input of said dummy comparator to form a comparator bias voltage.
Inventors
- 👤 Eric P. Etheridge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:18
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
86 words
An apparatus for generating a CMOS comparator bias voltage comprising: (a) a dummy comparator having a negative input and a positive input coupled together to receive a common mode reference voltage, a bias input, and an output; and (b) a bias amplifier having a positive input coupled to the output of said dummy comparator, a negative input for receiving a threshold reference voltage, and an output to form the CMOS comparator bias voltage, the output also being coupled to the bias input of said dummy comparator.
Claim 2
Independent Claim
86 words
An apparatus for generating a CMOS comparator bias voltage comprising: (a) a dummy comparator having a negative input and a positive input coupled together to receive a common mode reference voltage, a bias input, and an output; and (b) a bias amplifier having a positive input coupled to the output of said dummy comparator, a negative input for receiving a threshold reference voltage, and an output to form the CMOS comparator bias voltage, the output also being coupled to the bias input of said dummy comparator.
Claim 3
Dependent Claim
41 words
An apparatus for generating a CMOS comparator bias voltage as in claim 1 further comprising a CMOS inverter having an input and an output coupled together and to the negative input of said bias amplifier to form the threshold reference voltage.
Claim 4
Dependent Claim
42 words
An apparatus for generating a CMOS comparator bias voltage as in claim 1 wherein said bias amplifier comprises: (a) a bias voltage input; and (b) means for generating a bias voltage having a bias voltage output coupled to the bias voltage input.
Claim 5
Dependent Claim
291 words
An apparatus for generating a CMOS comparator bias voltage as in claim 1 wherein said bias amplifier comprises: (a) a first transistor of a first polarity type having a gate forming the positive input, a drain, and a source; (b) a second transistor of the first polarity type having a gate forming the negative input, a drain, and a source coupled to the source of said first transistor; (c) a third transistor of a second polarity type having a gate and a drain coupled together and to the drain of said first transistor, and a source; (d) a fourth transistor of the second polarity type having a gate and a drain coupled together and to the drain of said second transistor, and a source coupled to the source of said third transistor and to a first source of supply voltage; (e) a fifth transistor of the second polarity type having a gate coupled to the gate of said third transistor, a source coupled to the first source of supply voltage, and a drain; (f) a sixth transistor of the second polarity type having a gate and a drain coupled together and to the drain of said fifth transistor, and a source coupled to the first source of supply voltage; (g) a seventh transistor of the first polarity type having a gate and a drain coupled together and to the drain of said fifth transistor to form the output, and a source coupled to a second source of supply voltage; and (h) an eighth transistor of the first polarity type having a gate coupled to the gate of said seventh transistor, a drain coupled to the source of said first transistor, and a source coupled to the second source of supply voltage.
References Cited (Backward Citations)
US4524329A
Cited
DE3503942A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |