Random access memory including switching elements to limit the number of energized data in pairs

Claim 2

A random access memory comprising: a plurality of memory blocks, arranged two-dimensionally, each of said memory blocks comprising a plurality of memory cells; a plurality of pairs of data lines for transferring write-data to and read-data from said memory blocks; first switching means, responsive to an address signal, for connecting selected ones of said memory blocks to selected ones of said pairs of data lines; data input/output means, having fewer input terminals than the number of said pairs of data lines, for receiving write-data for said memory cells and for outputting read-data from said memory cells; and second switching means, coupled to said first switching means by said pairs of data lines and to said input/output means, for connecting said selected ones of said pairs of data lines to said data input/output means.

Claim 3

A random access memory according to claim 1, further comprising a column decoder for generating a first output signal to control operation of said first switching means, and a section decoder for generating a second output signal to control operation of said second switching means.

Claim 4

A random access memory according to claim 2, wherein address signals Ai to Ak are supplied to said column decoder and address signals Aj+1 to Ak, which are a part of said address signals Ai to Ak, are supplied to said second decoder.

Claim 5

A random access memory according to claim 1, further comprising a block decoder for generating a first output signal to control operation of said first switching means, and a section decoder for generating a second output signal to control operation of said section switching means.

Claim 6

A random access memory according to claim 4, wherein address signals Ai to Ak are supplied to said block decoder and said section decoder.

Claim 7

A random access memory comprising: a plurality of memory blocks, arranged two-dimensionally, each comprising a plurality of memory cells; a plurality of pairs of data lines for transferring input data to said memory cells; a plurality of pairs of second data lines coupled between said memory blocks; first switching means, responsive to an address signal, for connecting selected ones of said memory blocks to selected ones of said pairs of first data lines and for connecting said selected ones of said pairs of first data lines to selected ones of said pairs of second data lines; data input/output means for receiving write-data for said memory cells and for outputting read-data from said memory cells, said data input/output means having fewer input terminals than the number of pairs of said data lines; and second switching means, coupled to said first switching means by said pairs of second data lines and to said data input/output means, for connecting said selected pairs of second data lines to said data input/output means.

Claim 8

A random access memory comprising: a plurality of memory blocks, arranged two-dimensionally, each comprising a plurality of memory cells; a plurality of pairs of data lines for transferring input data to said memory cells; a plurality of pairs of second data lines coupled between said memory blocks; first switching means, responsive to an address signal, for connecting selected ones of said memory blocks to selected ones of said pairs of first data lines and for connecting said selected ones of said pairs of first data lines to selected ones of said pairs of second data lines; data input/output means for receiving write-data for said memory cells and for outputting read-data from said memory cells, said data input/output means having fewer input terminals than the number of pairs of said data lines; and second switching means, coupled to said first switching means by said pairs of second data lines and to said data input/output means, for connecting said selected pairs of second data lines to said data input/output means.

Claim 9

A random access memory according to claim 6, further comprising a switching decoder for generating a first output signal to control operation of said first switching means, and a section decoder for generating a second output signal to control operation of said second switching means.

Claim 10

A random access memory according to claim 7, wherein address signals Ai to Ak are supplied to said switching decoder, and address signals Aj+1 to Ak, which are part of address signals Ai to Ak, are supplied to said section decoder.

Claim 11

A random access memory according to claim 6 wherein said selected ones of said pairs of first data lines are coupled to selected ones of said memory cells in said selected ones of said memory blocks.

Claim 12

A random access memory comprising: a plurality of groups of n memory blocks, each of said blocks having a plurality of memory cells and where n is a positive integer; memory block selecting means for selecting one block from each group of blocks in accordance with a plurality of address signals; a plurality of data latch means for latching write-data for and read-data from each selected block; a plurality of pairs of data lines coupled to said latch means for transferring read-data from and write-data to each selected block; first switching means for connecting selected ones of said data latch means to selected ones of said pairs of data lines in response to a control signal; data input/output means, having fewer input terminals than the number of said pairs of data lines, for receiving write-data for and read-data from said memory blocks; and second switching means, coupled to said first switching means by said pairs of data lines and to said data input/output means, for connecting said selected data lines to said data input/output means.

Claim 13

A random access memory comprising: a plurality of groups of n memory blocks, each of said blocks having a plurality of memory cells and where n is a positive integer; memory block selecting means for selecting one block from each group of blocks in accordance with a plurality of address signals; a plurality of data latch means for latching write-data for and read-data from each selected block; a plurality of pairs of data lines coupled to said latch means for transferring read-data from and write-data to each selected block; first switching means for connecting selected ones of said data latch means to selected ones of said pairs of data lines in response to a control signal; data input/output means, having fewer input terminals than the number of said pairs of data lines, for receiving write-data for and read-data from said memory blocks; and second switching means, coupled to said first switching means by said pairs of data lines and to said data input/output means, for connecting said selected data lines to said data input/output means.

Claim 14

A random access memory according to claim 10, wherein said memory block selecting means includes a column decoder, and wherein said random access memory further comprises a section decoder for generating an output signal to control operation of said second switching means.

Claim 15

A random access memory according to claim 11, wherein address signals Ai to Ak are supplied to said column decoder and address signals Aj+1 to Ak, which are part of address signals Ai to Ak, are supplied to said section decoder.