Dram having pip capacitor inside a trench

Claim 2

A semiconductor memory device comprising: a silicon substrate; an insulating layer formed over said substrate and comprised of a first portion and a second portion; at least one monocrystalline silicon island formed within said insulating layer on the first portion thereof, separated from said silicon substrate by the first portion of said insulating layer and laterally spaced from one another by the second portion of said insulating layer, with at least one trench having one wall defined by a side of the at least one monocrystalline silicon island and extending into the first portion of said insulating layer, and having an opposite wall defined by the second portion of said insulating layer, the second portion of said insulating layer being disposed between monocrystalline silicon islands when there are two or more monocrystalline silicon islands; a lower electrode formed on the inner surface of each said at least one trench and making contact with said at least one monocrystalline silicon island; a dielectric film formed over said lower electrode; and an upper electrode formed over said dielectric film; wherein information is stored as charge in a capacitor comprising said lower electrode, said dielectric layer, and said upper electrode.

Claim 3

A semiconductor memory device as set forth in claim 1, wherein sides of said second portion of said insulating layer form parts of the walls of the at least one trench.

Claim 4

A semiconductor memory device as set forth in claim 1, wherein the top surface of the second portion of said insulating layer is substantially coplanar with the top surface of said at least one monocrystalline island.

Claim 5

A semiconductor memory device as set forth in claim 1, wherein said at least one trench is in the form of a quadrangular prism and upper parts of three sides of each said at least one trench are defined by said second portion of said insulating layer.

Claim 6

A semiconductor memory device as set forth in claim 1, wherein said at least one trench is formed at an end of said at least one monocrystalline silicon island.

Claim 7

A semiconductor memory device as set forth in claim 1, wherein said insulating layer is made of porous oxidized silicon.

Claim 8

A semiconductor dynamic memory device comprising: a silicon substrate; an insulating layer formed over said substrate and comprised of a first portion and a second portion; first and second conductive silicon islands formed within said insulating layer on the first portion thereof, separated from said silicon substrate by the first portion of said insulating layer and laterally spaced from one another by the second portion of said insulating layer, first and second MOS transistor regions having diffusion regions formed respectively in said first and second conductive silicon islands, first and second trenches disposed between said first and second conductive silicon islands, each having one wall defined by a side of one said first and second conductive silicon islands and each extending into the first portion of said insulating layer, and each having an opposite wall defined by the second portion of said insulating layer, the second portion of said insulating layer being disposed between said first and second conductive silicon islands; a lower electrode formed on the inner surface of each of said first and second trenches and making contact respectively with said first and second conductive silicon islands; a dielectric film formed over said lower electrode; and an upper electrode formed over said dielectric film; wherein information is stored as charge in a capacitor comprising said lower electrode, said dielectric layer, and said upper electrode.

Claim 9

A semiconductor dynamic memory device comprising: a silicon substrate; an insulating layer formed over said substrate and comprised of a first portion and a second portion; first and second conductive silicon islands formed within said insulating layer on the first portion thereof, separated from said silicon substrate by the first portion of said insulating layer and laterally spaced from one another by the second portion of said insulating layer, first and second MOS transistor regions having diffusion regions formed respectively in said first and second conductive silicon islands, first and second trenches disposed between said first and second conductive silicon islands, each having one wall defined by a side of one said first and second conductive silicon islands and each extending into the first portion of said insulating layer, and each having an opposite wall defined by the second portion of said insulating layer, the second portion of said insulating layer being disposed between said first and second conductive silicon islands; a lower electrode formed on the inner surface of each of said first and second trenches and making contact respectively with said first and second conductive silicon islands; a dielectric film formed over said lower electrode; and an upper electrode formed over said dielectric film; wherein information is stored as charge in a capacitor comprising said lower electrode, said dielectric layer, and said upper electrode.

Claim 10

A semiconductor dynamic memory device as set forth in claim 7, wherein said insulating layer is formed of silicon oxide.

Claim 11

A semiconductor dynamic memory device as set forth in claim 8, wherein the upper electrode has respective regions over said first and second trenches which are electrically coupled with each other.

Claim 12

A semiconductor dynamic memory device as set forth in claim 7, wherein said insulating layer is formed of porous silicon oxide.

Claim 13

A semiconductor dynamic memory device as set forth in claim 10, wherein the upper electrode has respective regions over said first and second trenches which are electrically coupled with each other.