Method of making a semiconductor ROM device

Claim 1

A method of manufacturing a read only memory semiconductor device comprising the steps of: forming a field insulation region in a semiconductor substrate of a first conductivity type to form a region of the first conductivity type for an element isolated from another region of the substrate; forming a first insulation film for gate insulation on the element region; forming a first conductive layer for a gate electrode on said gate insulation film; doping an impurity of a second conductivity type opposite to said first conductivity type into said element region, using as a mask said field insulation region and gate electrode, to form a pair of semiconductor regions of said second conductivity type; forming a second insulation film on the entire major surface of the semiconductor structure; forming a contact hole, in said second insulation film, leading to one of said pair of semiconductor regions; forming a second conductive layer of said second conductivity type functioning as an interconnection layer with a predetermined pattern on the entire major surface of the semiconductor structure, the second conductive layer contacting said one of the pair of semiconductor regions and extending onto that part of said second insulation film which is on said gate electrode; forming a third insulation film on the entire major surface of the semiconductor structure; forming a contact hole, in said third insulation film, leading to said second conductive layer according to the information to be stored; and forming a third conductive layer with a predetermined pattern on the entire major surface of semiconductor structure.

Claim 2

A method of manufacturing a read only memory semiconductor device comprising the steps of: forming a field insulation region in a semiconductor substrate of a first conductivity type to form a region of the first conductivity type for an element isolated from another region of the substrate; forming a first insulation film for gate insulation on the element region; forming a first conductive layer for a gate electrode on said gate insulation film; doping an impurity of a second conductivity type opposite to said first conductivity type into said element region, using as a mask said field insulation region and gate electrode, to form a pair of semiconductor regions of said second conductivity type; forming a second insulation film on the entire major surface of the semiconductor structure; forming a contact hole, in said second insulation film, leading to one of said pair of semiconductor regions; forming a second conductive layer of said second conductivity type functioning as an interconnection layer with a predetermined pattern on the entire major surface of the semiconductor structure, the second conductive layer contacting said one of the pair of semiconductor regions and extending onto that part of said second insulation film which is on said gate electrode; forming a third insulation film on the entire major surface of the semiconductor structure; forming a contact hole, in said third insulation film, leading to said second conductive layer according to the information to be stored; and forming a third conductive layer with a predetermined pattern on the entire major surface of semiconductor structure.