Process for the digital to analog conversion of digital information in bipolar analog signals

Claim 2

A process for the digital to analog conversion of digital information in bipolar analog signals by means of a network comprising capacitors which are binary-stepped in their capacitance and a further capacitor having the same capacitance as the lowest value capacitor, whereof the lower terminals, depending on the binary value of the digital information bit to which said lower terminals are respectively allocated, are coupled to ground potential or to a reference voltage source providing voltage of one polarity only and thereby codetermine or do not codetermine the value of the network output voltage representing the analog signal after a charge has been redistributed, wherein the same capacitors always take part in the charge redistribution for generating positive and negative analog values of the same amount.

Claim 3

A process in accordance with claim 1 further characterized in that, in a preparatory sequence, upper interconnected plates of the capacitors of the network, are switched to ground potential, and, depending upon whether the value of the sign bit of the digital information to be converted requires the generation of a positive or negative analog value, the other plates representing the separate, lower terminals of the capacitors are applied to the reference voltage source or ground potential, and in a subsequent step, during which the charge is redistributed, the upper interconnected plates of all capacitors are switched off from ground potential and the separate lower terminals of the capacitors allocated to the bits having the binary value of 1 are switched to ground potential or to the reference voltage source, whereas the plates which represent the lower terminals of the remaining capacitors remain switched to the reference voltage source or to ground potential.

Claim 4

A process in accordance with claim 1 further characterized in that, in a preparatory sequence, upper interconnected plates of the capacitors (C through C/16), are switched to ground potential, and, depending upon whether the value of the sign bit of the digital information to be converted requires a positive or a negative analog value, the lower plates of the capacitor (C), allocated to the sign bit, and the plates of those capacitors (e.g., C/4, C/8) allocated to the bits having the binary value of 0, as well as the plates of a further capacitor (C'/16), said capacitor having the same capacitance as the capacitor (C/16) allocated to the lowest-order bit of the digital information to be converted, are switched to ground potential or to the reference voltage source (V ref ), and the lower plates of the capacitors (e.g., C/2, C/16), which are allocated to the bits having the binary value of 1, are oppositely switched to the reference voltage source or to ground potential, and in a subsequent step, which serves to redistribute the charge, the interconnected upper plates of the capacitors (C through C'/16) are switched off from ground potential, and the lower plates of the capacitors (for example, C/2, C/16), allocated to the bits having the binary value of 1, are switched similarly to the others to ground potential or to the reference voltage source (V ref ).