MOS semiconductor circuit

Claim 2

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and the output node of one of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; and a current control circuit including a polysilicon resistor coupled to said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor.

Claim 3

The MOS semiconductor circuit according to claim 1, wherein said first MOS transistor circuit has a plurality of first MOS transistors respectively coupled between said first voltage terminal and said output nodes of said logical circuits.

Claim 4

The MOS semiconductor circuit according to claim 1, wherein said MOS semiconductor circuit further comprises a second MOS transistor circuit having at least one third MOS transistor coupled between said second voltage terminal and said output nodes of said logical circuits; and wherein said current control circuit has a fourth MOS transistor having the same conductivity type as said third MOS transistor and having a gate coupled to a gate of said third MOS transistor and a drain coupled to said gate of said fourth MOS transistor, and a current source coupled between drains of said second and fourth MOS transistor to provide a predetermined current between said source and drain of said fourth MOS transistor.

Claim 5

The MOS semiconductor circuit according to claim 3, wherein said current control circuit comprises a polysilicon resistor.

Claim 6

The MOS semiconductor circuit according to claim 3, wherein said second MOS transistor circuit has a plurality of fifth MOS transistors respectively coupled between said second voltage terminal and said output nodes of said logical circuits.

Claim 7

The MOS semiconductor circuit according to claim 1, wherein said first and second MOS transistors have the same channel length.

Claim 8

The MOS semiconductor circuit according to claim 1, wherein said first and second MOS transistors have the same channel width.

Claim 9

The MOS semiconductor circuit according to claim 1, wherein each of said logical circuits comprises an N-channel MOS inverter.

Claim 10

The MOS semiconductor circuit according to claim 1, further comprising capacitors respectively coupled between said second voltage terminal and output nodes of said logical circuits.

Claim 11

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and one of the output nodes of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; and a current control circuit, coupled to said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor; wherein said logical circuits comprise an inverter circuit including at least two cascade-connected inverters, NOR and NAND gates for receiving in-phase signals from both input and output terminals of said inverter circuit, and a wave shaping circuit for generating output signals, corresponding to said output signals from said inverter circuit, in response to output signals of said NOR and NAND gates.

Claim 12

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and one of the output nodes of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; and a current control circuit, coupled to said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor; wherein said logical circuits comprise an inverter circuit including at least two cascade-connected inverters, NOR and NAND gates for receiving in-phase signals from both input and output terminals of said inverter circuit, and a wave shaping circuit for generating output signals, corresponding to said output signals from said inverter circuit, in response to output signals of said NOR and NAND gates.

Claim 13

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected inverters, an output terminal of the last stage of said inverters being coupled to an input terminal of the first stage of said inverters, thereby constituting a ring oscillator; a first MOS transistor circuit having a least one first MOS transistor coupled between said first voltage terminal and the output node of one of said inverters; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and drain coupled to said gate of said second MOS transistor; a current control circuit, coupled ot said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor; NOR and NAND gates for receiving in-phase output signals of two of said inverters; and a wave shaping circuit for generating output signals, corresponding to said output signals of said two inverters, in response to output signals of said NOR and NAND gates.

Claim 14

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected inverters, an output terminal of the last stage of said inverters being coupled to an input terminal of the first stage of said inverters, thereby constituting a ring oscillator; a first MOS transistor circuit having a least one first MOS transistor coupled between said first voltage terminal and the output node of one of said inverters; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and drain coupled to said gate of said second MOS transistor; a current control circuit, coupled ot said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor; NOR and NAND gates for receiving in-phase output signals of two of said inverters; and a wave shaping circuit for generating output signals, corresponding to said output signals of said two inverters, in response to output signals of said NOR and NAND gates.

Claim 15

The MOS semiconductor circuit according to claim 11, wherein said wave shaping circuit has a P-channel MOS transistor having a gate coupled to an output terminal of said NAND gate, and an N-channel MOS transistor having a gate coupled to an output terminal of said NOR gate, said P-channel MOS transistor and said N-channel MOS transistor being coupled in series between said first and second voltage terminals.

Claim 16

The MOS semiconductor circuit according to claim 12, further comprising feedback means, coupled to an output terminal of said wave shaping circuit, for stabilizing a potential of said output terminal of said wave shaping circuit.

Claim 17

A MOS semiconductor circuit comprising: a ring oscillator comprising an odd number of inverters; a plurality of NOR and NAND gates for receiving in-phase output signals from two of said inverters; and a wave shaping circuit for generating output signals, corresponding to said output signals of said two inverters, in response to output signals of said NOR and NAND gates; wherein said wave shaping circuit has a series-connected P-channel MOS transistor and an N-channel MOS transistor, said P-channel MOS transistor having a gate coupled to an output terminal of said NAND gate, and said N-channel MOS transistor having a gate couple to an output terminal of said NOR gate.

Claim 18

A MOS semiconductor circuit comprising: a ring oscillator comprising an odd number of inverters; a plurality of NOR and NAND gates for receiving in-phase output signals from two of said inverters; and a wave shaping circuit for generating output signals, corresponding to said output signals of said two inverters, in response to output signals of said NOR and NAND gates; wherein said wave shaping circuit has a series-connected P-channel MOS transistor and an N-channel MOS transistor, said P-channel MOS transistor having a gate coupled to an output terminal of said NAND gate, and said N-channel MOS transistor having a gate couple to an output terminal of said NOR gate.

Claim 19

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and the output node of one of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; a second MOS transistor circuit having at least one third MOS transistor coupled between said second voltage terminal and said output nodes of said logical circuits; a fourth MOS transistor having the same conductivity type as said third MOS transistor and having a gate coupled to a gate of said third MOS transistor and a drain coupled to said gate of said fourth MOS transistor; and a current control circuit having a current source coupled between said drains of said second and fourth MOS transistors.

Claim 20

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and the output node of one of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; a second MOS transistor circuit having at least one third MOS transistor coupled between said second voltage terminal and said output nodes of said logical circuits; a fourth MOS transistor having the same conductivity type as said third MOS transistor and having a gate coupled to a gate of said third MOS transistor and a drain coupled to said gate of said fourth MOS transistor; and a current control circuit having a current source coupled between said drains of said second and fourth MOS transistors.

Claim 21

The MOS semiconductor circuit according to claim 15, wherein said current control circuit has a plurality of series-connected diodes.

Claim 22

The MOS semiconductor circuit according to claim 15, wherein said current source has parallel-connected fifth MOS transistors of a different conductivity type.

Claim 23

The MOS semiconductor circuit according to claim 15, wherein said second MOS transistor circuit has a plurality of fifth MOS transistors respectively coupled between said second voltage terminal and said output nodes of said logical circuits.

Claim 24

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and the output node of one of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; and a current control circuit including a diffusion resistor coupled to said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor.

Claim 25

A MOS semiconductor circuit comprising: first and second voltage terminals; cascade-connected logical circuits; a first MOS transistor circuit having at least one first MOS transistor coupled between said first voltage terminal and the output node of one of said logical circuits; a second MOS transistor having the same conductivity type as said first MOS transistor and having a gate coupled to a gate of said first MOS transistor and a drain coupled to said gate of said second MOS transistor; and a current control circuit including a diffusion resistor coupled to said drain of said second MOS transistor, for causing a predetermined current to flow through the source-drain path of said second MOS transistor.

Claim 26

The MOS semiconductor circuit according to claim 19, wherein said current control circuit has a diode coupled in parallel with said resistor.