Apparatus for recording and/or reproducing optical cards

Claim 1

An apparatus for recording optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable, comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting an error correction code; an encoder means including means for generating checking words on the basis of said error correction code and adding said checking words to output signals from said data source, and a scramble processing circuit for scramble processing output signals from said encoder, said scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, said scramble processing circuit comprising a first random access memory for storing data received from said encoder with said checking words, a second random access memory for said scramble processing, a read only memory for generating writing addressed for writing to said second random access memory, and counter means for generating read addresses for said first random access memory and said read only memory, the output signals from said encoder means being arranged in the form of blocks at intervals of the number of words allocated to one data track.

Claim 2

An apparatus for recording optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable, comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting an error correction code; an encoder means including means for generating checking words on the basis of said error correction code and adding said checking words to output signals from said data source, and a scramble processing circuit for scramble processing output signals from said encoder, said scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, said scramble processing circuit comprising a first random access memory for storing data received from said encoder with said checking words, a second random access memory for said scramble processing, a read only memory for generating writing addressed for writing to said second random access memory, and counter means for generating read addresses for said first random access memory and said read only memory, the output signals from said encoder means being arranged in the form of blocks at intervals of the number of words allocated to one data track.

Claim 5

An apparatus for recording and reproducing optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable, comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting an error correction code; an encoder means including means for generating checking words on the basis of said error correction code and adding said checking words to output signals from said data source, and a scramble processing circuit for scramble processing output signals from said encoder, comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction; a decoder means including a descramble processing circuit for implementing a descramble processing with respect to the output signals from a card reader and a decoder for implementing an error correction processing with respect to the output signals from said descramble processing circuit; said scramble processing circuit comprising a first random access memory for storing data received from said encoder with said checking words, a second random access memory for scramble processing, a first read only memory for generating write address for writing to said second random access memory, and first counter means for generating read addresses for said first random access memory and said first read only memory; said descramble processing circuit further Comprising a third random access memory for storing read-out data, a fourth random access memory for said descramble processing, a second read only memory for generating write addresses for writing into said fourth random access memory, and second counter means for generating read addresses for reading from said third random access memory and said second read only memory.

Claim 6

An apparatus for recording and reproducing optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable, comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting an error correction code; an encoder means including means for generating checking words on the basis of said error correction code and adding said checking words to output signals from said data source, and a scramble processing circuit for scramble processing output signals from said encoder, comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction; a decoder means including a descramble processing circuit for implementing a descramble processing with respect to the output signals from a card reader and a decoder for implementing an error correction processing with respect to the output signals from said descramble processing circuit; said scramble processing circuit comprising a first random access memory for storing data received from said encoder with said checking words, a second random access memory for scramble processing, a first read only memory for generating write address for writing to said second random access memory, and first counter means for generating read addresses for said first random access memory and said first read only memory; said descramble processing circuit further Comprising a third random access memory for storing read-out data, a fourth random access memory for said descramble processing, a second read only memory for generating write addresses for writing into said fourth random access memory, and second counter means for generating read addresses for reading from said third random access memory and said second read only memory.

Claim 9

An apparatus for recording optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable, comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting first and second error correction codes; an encoder means including first encoder means for generating checking words on the basis of said first error correction code and adding said checking words to output signals from said source, a first scramble processing circuit for implementing a first scramble processing with respect to output signals from said first encoder, a second encoder for generating checking words on the basis of said second error correction code and adding said checking words to output signals from said first scramble processing circuit, and a second scramble processing circuit for implementing second scramble processing with respect to output signals from said second encoder, said first scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at position of a word number of which the phase is shifted by one word from the number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, and said second scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track and opposite to that at the time of said first scramble processing, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, said first and second scramble processing circuits including a first random access memory for storing data from said encoder with said checking words, a second random access memory for said scramble processing, a read only memory for generating write addresses for writing to said second random access memory, and counter means for generating read addresses for reading from said first random access memory and said read only memory, the output signals from said encoder means being arranged in the form of blocks at intervals of a number of words allocated to one data track.

Claim 10

An apparatus for recording optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable, comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting first and second error correction codes; an encoder means including first encoder means for generating checking words on the basis of said first error correction code and adding said checking words to output signals from said source, a first scramble processing circuit for implementing a first scramble processing with respect to output signals from said first encoder, a second encoder for generating checking words on the basis of said second error correction code and adding said checking words to output signals from said first scramble processing circuit, and a second scramble processing circuit for implementing second scramble processing with respect to output signals from said second encoder, said first scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at position of a word number of which the phase is shifted by one word from the number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, and said second scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track and opposite to that at the time of said first scramble processing, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, said first and second scramble processing circuits including a first random access memory for storing data from said encoder with said checking words, a second random access memory for said scramble processing, a read only memory for generating write addresses for writing to said second random access memory, and counter means for generating read addresses for reading from said first random access memory and said read only memory, the output signals from said encoder means being arranged in the form of blocks at intervals of a number of words allocated to one data track.

Claim 14

An apparatus for recording and reproducing optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting first and second error correction codes; an encoder means including first encoder means for generating checking words on the basis of said first error correction code and adding said checking words to output signals from said source, a first scramble processing circuit for implementing a first scramble processing with respect to output signals from said first encoder, a second encoder for generating checking words on the basis of said second error correction code and adding said checking words to output signals from said first scramble processing circuit, and a second scramble processing circuit for implementing a second scramble processing with respect to output signals from said second encoder, said first scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, and said second scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track and opposite to that at the time of said first scramble processing, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction; a reader for said optical record cards; and a decoder means including a second descramble processing circuit for implementing a second descramble processing corresponding to said second scramble processing with respect to the output signals from said reader, a second decoder for implementing a second error correction processing corresponding to said second error correction code with respect to the output signals from said second descramble processing circuit, a first descramble processing corresponding to said first scramble processing with respect to output signals from said second decoder, and a first decoder for implementing a first error correction processing corresponding to said first error correction code with respect to output signals from said first descramble processing circuit, said first and second scramble processing circuits including a first random access memory for storing data for which the error correction code processing has been implemented by the addition of checking words, a second random access memory for scramble processing, a first read only memory for generating write addresses for writing to said second random access memory, and first counter means for generating read addresses for said first random access memory and said first read only memory, said first and second descramble processing circuits including a third random access memory for storing read-out data, a fourth random access memory for descramble processing, a second read only memory for generating write addresses for writing into said fourth random access memory, and second counter means for generating read addresses for reading from said third random access memory and said second read only memory.

Claim 15

An apparatus for recording and reproducing optical record cards having optical recording media for storing recorded information data signals as a plurality of data tracks parallel to one another in the form of pit patterns so as to be optically readable comprising: an information data source for producing said information data signals to be recorded on each said data tracks; means for manifesting first and second error correction codes; an encoder means including first encoder means for generating checking words on the basis of said first error correction code and adding said checking words to output signals from said source, a first scramble processing circuit for implementing a first scramble processing with respect to output signals from said first encoder, a second encoder for generating checking words on the basis of said second error correction code and adding said checking words to output signals from said first scramble processing circuit, and a second scramble processing circuit for implementing a second scramble processing with respect to output signals from said second encoder, said first scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction, and said second scramble processing circuit comprising means for arranging the words so that each word is delayed by two words in the data track direction and by k tracks, where k is an integer, in the direction perpendicular to the data track and opposite to that at the time of said first scramble processing, and for placing the word at a position of a word number of which the phase is shifted by one word from the word number at the head of the block when the word that has reached the end of the data track is to be wrapped around to the other end and delayed, and then delaying each word by two words in the data track direction; a reader for said optical record cards; and a decoder means including a second descramble processing circuit for implementing a second descramble processing corresponding to said second scramble processing with respect to the output signals from said reader, a second decoder for implementing a second error correction processing corresponding to said second error correction code with respect to the output signals from said second descramble processing circuit, a first descramble processing corresponding to said first scramble processing with respect to output signals from said second decoder, and a first decoder for implementing a first error correction processing corresponding to said first error correction code with respect to output signals from said first descramble processing circuit, said first and second scramble processing circuits including a first random access memory for storing data for which the error correction code processing has been implemented by the addition of checking words, a second random access memory for scramble processing, a first read only memory for generating write addresses for writing to said second random access memory, and first counter means for generating read addresses for said first random access memory and said first read only memory, said first and second descramble processing circuits including a third random access memory for storing read-out data, a fourth random access memory for descramble processing, a second read only memory for generating write addresses for writing into said fourth random access memory, and second counter means for generating read addresses for reading from said third random access memory and said second read only memory.