Polynomial operator in galois fields and a digital signal processor comprising an operator of this type

Claim 1

A polynomial operator in Galois fields organized at three successive levels: a first level for the selection of operands comprising a multiplexing circuit, with three Balois value outputs; a so-called "pipeline" level, comprising three memory registers having three multiple inputs connected to the outputs of the multiplexing circuit, to memorize three operands, along with three associated outputs; and a calculating level comprising a multiplier/adder circuit in said Galois fields, the said circuit comprising two multiplier inputs, connected to the outputs of two of the memory registers, one adder input, connected to the output of the third memory register, the multiplier/adder circuit always performing the calculation X+(Y×Z) where + and × represent addition and multiplication in said Galois fields, said multiplier/adder circuit outputting a result output; and wherein the inputs of the multiplexing circuit are inputs of operands to receive Galois values from outside the operator, with, in addition, at least one input connected to the output of one of the memory registers, and one input connected to the result output of the multiplier/adder, the selection of one of the three inputs of the multiplexing circuit being programmed so that the calculating instruction X+(Y×Z) is unchanged regardless of the type of polynomial operation to be performed in a particular Galois field.