Common resource arbitration circuit having asynchronous access requests and timing signal used as clock input to register and mask signal to priority network

Claim 1

Arbitration circuit for granting common resource (BUS 8, MM4) access to one among a plurality of units (CPU, IMDC, DMA) competing for access to said common resource by means of asynchronous access request signals (CPUR, IMDCR, DMAR) having a predetermined relative priority to each other, comprising: a register having inputs for receiving said plurality of asynchronous access request signals, a single clock input receiving a single periodic timing square wave signal, the access request signals present at said inputs being latched into said register at each transition of said timing signal from a first electrical level to a second level, a plurality of arbitration logical networks, each one related to one unit of said plurality, each having an output for outputting a related resource grant signal (CPUG, IMDCG, DMAG) a plurality of holding logics, each one related to one of said arbitration logical networks and to one of said units, each one having first input connected to the output of the related arbitration logical network and holding and transferring to an output the resource grant signal received as input, each of said arbitration logical networks having inputs connected to outputs of said register and to the output of the holding logic related to each of the others of said arbitration logical networks, and generating said related resource grant signal at its output if no other resource grant signals are received as inputs from the output of the holding logics related to all other arbitration logical networks, if an access request signal from the related unit is latched in said register and if no access request signals from other units having higher priority are latched in said register, each of said arbitration logical networks receiving further as input, said single periodic time square wave signal for inhibiting the generation of said related resource grant signal at its output during the half period in which said timing signal is at said second level, each of said holding logics, holding and transferring to its output the resource grant signal received as input, in the half period in which said timing signal is at said second level.