US4851891A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate array having transistor buried in interconnection region
Assignee: Fujitsu Ltd
•
Filing: 1988-02-09
•
Granted: 1989-07-25
•
Expires: 2008-02-09
Abstract
Abstract A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.
Inventors
- 👤 Hajime Kubosawa
- 👤 Mitsugu Naitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10W; H10W20/00; H10W20/20; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
268 words
A gate array comprising: a semiconductor substrate; a plurality of mutually parallel basic cell columns including a plurality of basic cells formed on said semiconductor substrate, each of said basic cells comprising a pair of a first p-channel transistor and a first n-channel transistor; a plurality of interconnection regions each formed between two mutually adjacent ones of said basic cell columns; and specific cells buried in one of a plurality of predetermined ones of said interconnection regions, each of said specific cells comprising at least a second p-channel transistor and a second n-channel transistor forming a transmission gate, said second n-channel transistor having an n-type source/drain region and a first gate electrode, said second p-channel transistor having a p-type source/drain region and a second gate electrode, said n-type source/drain region having a first portion extending parallel to said basic cell columns and a second portion extending in a direction perpendicular to said basic cell columns from one end of said first portion, said p-type source/drain region having a third portion extending parallel to said basic cell columns and a fourth portion extending in a direction perpendicular to said basic cell columns from one end of said third portion, said n-type source/drain region and said p-type source/drain region substantially confronting each other in a central portion of said specific cell so that a large portion of said n-type source/drain region and a large portion of said p-type source/drain region are respectively sectioned by a center line of said specific cell parallel to said basic cell columns, said first and second gate electrodes extending parallel to said basic cell columns.
Claim 2
Dependent Claim
268 words
A gate array comprising: a semiconductor substrate; a plurality of mutually parallel basic cell columns including a plurality of basic cells formed on said semiconductor substrate, each of said basic cells comprising a pair of a first p-channel transistor and a first n-channel transistor; a plurality of interconnection regions each formed between two mutually adjacent ones of said basic cell columns; and specific cells buried in one of a plurality of predetermined ones of said interconnection regions, each of said specific cells comprising at least a second p-channel transistor and a second n-channel transistor forming a transmission gate, said second n-channel transistor having an n-type source/drain region and a first gate electrode, said second p-channel transistor having a p-type source/drain region and a second gate electrode, said n-type source/drain region having a first portion extending parallel to said basic cell columns and a second portion extending in a direction perpendicular to said basic cell columns from one end of said first portion, said p-type source/drain region having a third portion extending parallel to said basic cell columns and a fourth portion extending in a direction perpendicular to said basic cell columns from one end of said third portion, said n-type source/drain region and said p-type source/drain region substantially confronting each other in a central portion of said specific cell so that a large portion of said n-type source/drain region and a large portion of said p-type source/drain region are respectively sectioned by a center line of said specific cell parallel to said basic cell columns, said first and second gate electrodes extending parallel to said basic cell columns.
Claim 3
Dependent Claim
47 words
A gate array as claimed in claim 1, wherein said basic cells have an elongated shape extending generally in a predetermined direction perpendicular to said basic cell columns, and said specific cells having an elongated shape extending generally in a direction parallel to said basic cell columns.
Claim 4
Dependent Claim
69 words
A gate array as claimed in claim 1, wherein said second p-channel transistor and said second n-channel transistor of said specific cells each have a gate extending parallel to said basic cell columns, said gate having a channel width-to-length ratio which is greater than or equal to two times a channel width-to-length ratio of gates of said first p-channel transistors and said first n-channel transistors of said basic cells.
Claim 5
Dependent Claim
39 words
A gate array as claimed in claim 1, further comprising a plurality of cells provided on a peripheral portion of said semiconductor substrate for forming an interface between an external circuit and the cells formed on said semiconductor substrate.
Claim 6
Dependent Claim
50 words
A gate array as claimed in claim 1, further comprising an interconnection for making internal connections within said specific cell and interconnections for power source voltages respectively arranged in a central portion of said specific cell, said interconnections for the power source voltages being parallel to said basic cell columns.
Claim 7
Dependent Claim
17 words
A gate array as claimed in claim 5, wherein said interconnections are provided in a single level.
Claim 8
Dependent Claim
264 words
A gate array comprising: a semiconductor substrate; a plurality of mutually parallel basic cell columns each including a plurality of basic cells formed on said semiconductor substrate, each of said basic cells including a pair of a first p-channel transistor and a first n-channel transistor; a plurality of interconnection regions each formed between two mutually adjacent ones of said basic cell columns; and specific cells buried in one of a plurality of predetermined ones of said interconnection regions, each of said specific cells including at least a second p-channel transistor and a second n-channel transistor forming a transmission gate, said n-channel transistor including an n-type source/drain region and a first gate electrode and said second p-channel transistor including a p-type source/drain region and a second gate electrode, said p-type source/drain region and said n-type source/drain region substantially confronting each other in a central portion of said specific cell so that a large portion of said p-type source/drain region and a large portion of said n-type source/drain region are respectfully sectioned by a center line of said specific cell parallel to said basic cell column, said n-type source/drain region including a first portion extending parallel to said basic cell columns and a pair of second portions extending in a direction intersecting the center line form both ends of the first portion, and said p-type source/drain region including a third portion extending parallel to said basic cell columns and a fourth portion extending from one end of said third portion so as to intersect the center line between the second portions of said n-type source/drain region.
Claim 9
Dependent Claim
264 words
A gate array comprising: a semiconductor substrate; a plurality of mutually parallel basic cell columns each including a plurality of basic cells formed on said semiconductor substrate, each of said basic cells including a pair of a first p-channel transistor and a first n-channel transistor; a plurality of interconnection regions each formed between two mutually adjacent ones of said basic cell columns; and specific cells buried in one of a plurality of predetermined ones of said interconnection regions, each of said specific cells including at least a second p-channel transistor and a second n-channel transistor forming a transmission gate, said n-channel transistor including an n-type source/drain region and a first gate electrode and said second p-channel transistor including a p-type source/drain region and a second gate electrode, said p-type source/drain region and said n-type source/drain region substantially confronting each other in a central portion of said specific cell so that a large portion of said p-type source/drain region and a large portion of said n-type source/drain region are respectfully sectioned by a center line of said specific cell parallel to said basic cell column, said n-type source/drain region including a first portion extending parallel to said basic cell columns and a pair of second portions extending in a direction intersecting the center line form both ends of the first portion, and said p-type source/drain region including a third portion extending parallel to said basic cell columns and a fourth portion extending from one end of said third portion so as to intersect the center line between the second portions of said n-type source/drain region.
Claim 10
Dependent Claim
66 words
A gate array as claimed in claim 7, wherein said first gate electrode being provided on said n-type source/drain region and extending parallel to said basic cell columns to approximately divide said first portion into two parts, and said second gate electrode being provided on said p-type source/drain region and extending parallel to said basic cell columns to approximately divide said third portion into two parts.
Claim 11
Dependent Claim
56 words
A gate array as claimed in claim 7, further comprising a contact region provided between said second portion of said n-type source/drain region and said fourth portion of said p-type source/drain region, and interconnections for supplying power source voltages running parallel to said basic cell columns, said contact region being connected to one of said interconnections.
Claim 12
Dependent Claim
74 words
A gate array as claimed in claim 7, further comprising an interconnection for connecting one of said pair of second portions of said n-type source/drain region and said fourth portion of said p-type source/drain region and an interconnection for connecting the other one of said second portions of said n-type source/drain region and said fourth portion of said p-type source/drain region, said interconnections lie on a single level parallel to said basic cell columns.
Claim 13
Dependent Claim
50 words
A gate array as claimed in claim 1, further comprising an interconnection for making internal connections within said specific cell and interconnections for power source voltages respectively arranged in a central portion of said specific cell, said interconnections for the power source voltages running parallel to said basic cell columns.
Claim 14
Dependent Claim
17 words
A gate array as claimed in claim 11, wherein said interconnections are provided in a single level.
Claim 15
Dependent Claim
49 words
A gate array as set forth in claim 7, wherein said basic cells have an elongated shape extending substantially in a predetermined direction perpendicular to said basic cell columns, and wherein said specific cells have an elongated shape extending substantially in a direction parallel to said basic cell columns.
Claim 16
Dependent Claim
70 words
A gate array as set forth in claim 7, wherein each said second p-channel transistor and said second n-channel transistor of said specific cells has a gate extending parallel to said basic cell columns, said gate having a channel width-to-length ratio which is greater than or equal to two times a channel width-to-length ratio of gates of said first p-channel transistor and said first n-channel transistors of said basic cells.
Claim 17
Dependent Claim
40 words
A gate array as set forth in claim 7, further comprising a plurality of cells provided on a peripheral portion of said semiconductor substrate for forming an interface between an external circuit and the cells formed on said semiconductor substrate.
Claim 18
Dependent Claim
50 words
A gate array as set forth in claim 7, further comprising an interconnection for making internal connections within said specific cells and for power source voltages, respectively, arranged in a central portion of said specific cell, said interconnection for the power source voltages being parallel to said basic cell columns.
Claim 19
Dependent Claim
18 words
A gate array as set forth in claim 16, wherein said interconnections are provided in a single level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |