Patent US4670385A successfully refreshed from Google Patents.
Patent US4851844A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4851844A Expired / Lapsed US ⏱️ 0.0 years remaining

D/A converter with switched capacitor control

Assignee: Sony Corp
•
Filing: 1986-05-09
•
Granted: 1989-07-25
•
Expires: 2006-05-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PCT No. PCT/JP86/00240 Sec. 371 Date Jan. 9, 1987 Sec. 102(e) Date Jan. 9, 1987 PCT Filed May 9, 1986 PCT Pub. No. WO86/06896 PCT Pub. Date Nov. 20, 1986.There are provided a current-voltage converting means (22) for converting a constant current from a constant current supplying circuit into a voltage, an integration circuit (26), a switched capacitor (23) arranged between the current-voltage converting means (22) and the integration circuit (26) for controlling the charge amount supplied to the integration circuit, and first and second control signal generating circuits (28, 31) respectively having counters (29, 32) and comparators (30, 33) and supplied with first and second digital input signals for controlling switching frequency of the switched capacitor (23) to thereby generate, at an output of the integration circuit (26), an analog signal proportional to a product of the first and second digital input signals, to thereby simplify the circuit configuration and reduce the production cost.

Inventors

  • 👤 Kenzo Akagiri

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 15:03
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; G; G06; G06J; G06J1/00

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 202 words
A D/A converter comprising first digital signal inputting means, a second digital signal inputting means, a constant voltage generating circuit, an integration circuit, a switched capacitor circuit arranged between said constant voltage generating circuit and said integration circuit, said switched capacitor circuit connected to receive an input signal from said constant voltage generating circuit and to provide a pulsed output signal to said integration circuit with said pulsed output signal having a controllable duty cycle, a first control circuit for controlling the duty cycle of said switched capacitor circuit by said first digital input signal, and a second control circuit for controlling the repetition of the duty cycle of said switched capacitor circuit by said second digital input signal, which generates, at an output of said integration circuit, an analog signal proportional to a product of said first and second digital input signals, and clock generator means for supplying clock signals to said first control circuit at a pulse repetition rate of f and for supplying clock signals to said second control circuit at a pulse repetition rate of f/n, where n is a function of the period of operation of said switched capacitor circuit, as controlled by said first control circuit.
Claim 2
Dependent Claim 202 words
A D/A converter comprising first digital signal inputting means, a second digital signal inputting means, a constant voltage generating circuit, an integration circuit, a switched capacitor circuit arranged between said constant voltage generating circuit and said integration circuit, said switched capacitor circuit connected to receive an input signal from said constant voltage generating circuit and to provide a pulsed output signal to said integration circuit with said pulsed output signal having a controllable duty cycle, a first control circuit for controlling the duty cycle of said switched capacitor circuit by said first digital input signal, and a second control circuit for controlling the repetition of the duty cycle of said switched capacitor circuit by said second digital input signal, which generates, at an output of said integration circuit, an analog signal proportional to a product of said first and second digital input signals, and clock generator means for supplying clock signals to said first control circuit at a pulse repetition rate of f and for supplying clock signals to said second control circuit at a pulse repetition rate of f/n, where n is a function of the period of operation of said switched capacitor circuit, as controlled by said first control circuit.
Claim 3
Dependent Claim 63 words
A D/A converter according to claim 1, in which said first control circuit comprises a first counter which is supplied with a clock pulse, a first comparator which compares the counted value of said counter with said first digital input signal, and a first gate circuit which controls the duty cycle of said switched capacitor circuit by an output signal from said comparator.
Claim 4
Dependent Claim 75 words
A D/A converter according to claim 1, in which said second control circuit comprises a second counter which is supplied with a frequency-divided output of said clock pulse as its clock pulse, a second comparator which compares the counted value of said counter with said second digital input signal, and a second gate circuit which controls the repetition of the duty cycle of said switched capacitor circuit by an output signal from said second comparator.
Claim 5
Dependent Claim 24 words
A D/A converter according to claim 3, in which said first digital input signal represents a mantissa portion outputted from a floating-point processing circuit.
Claim 6
Dependent Claim 24 words
A D/A converter according to claim 4, in which said second digital input signal represents an exponent portion outputted from said floating-point processing circuit.
Claim 7
Dependent Claim 64 words
(After being amended) A D/A converter according to claim 1, in which said constant voltage generating circuit is formed of a current-voltage converting means which converts a constant current generated from a constant current supplying circuit into a constant voltage, and the current value of said constant current supplying circuit is varied in response to a digital value of said first digital input signal.

References Cited (Backward Citations)

US3422423A Cited
JPS5620329A Cited
JPS58115925A Cited
JPH0534772A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-24 1993-01-23 1993-07-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-24 1997-01-23 1997-07-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-24 2001-01-23 2001-07-25 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag