Computer video demultiplexer

Claim 1

A system for generating high horizontal resolution video output frames having a plurality of horizontal lines from low resolution video input frames having a plurality of horizontal lines, comprising: means for receiving video input data representing a plurality of low resolution video input frames; means for storing said plurality of low resolution video input frames at a first clock rate; means for combining corresponding lines of selected ones of said plurality of stored frames to form a single horizontal line; and means for outputting each said formed single horizontal line at a second clock rate substantially greater than said first clock rate thereby generating a horizontal line output having a higher resolution than the horizontal lines of said low resolution input frames.

Claim 2

A system for generating high horizontal resolution video output frames having a plurality of horizontal lines from low resolution video input frames having a plurality of horizontal lines, comprising: means for receiving video input data representing a plurality of low resolution video input frames; means for storing said plurality of low resolution video input frames at a first clock rate; means for combining corresponding lines of selected ones of said plurality of stored frames to form a single horizontal line; and means for outputting each said formed single horizontal line at a second clock rate substantially greater than said first clock rate thereby generating a horizontal line output having a higher resolution than the horizontal lines of said low resolution input frames.

Claim 3

A method of generating high resolution video output frames having horizontal lines from lower resolution video input frame shaving horizontal lines, comprising: receiving video input data representing a plurality of low resolution video input frames; storing a plurality of said lower resolution video input frames at a first clock rate; combining corresponding lines of selected ones of said plurality of stored frames to form a single horizontal line of video data; outputting each of said formed single horizontal lines at a second clock rate substantially greater than said first clock rate thereby producing high resolution video output frames from said formed horizontal lines having a substantially higher resolution than the horizontal lines of said low resolution input frames; and displaying a single frame of video data from a plurality of said formed single horizontal lines.

Claim 4

A method of generating high resolution video output frames having horizontal lines from lower resolution video input frame shaving horizontal lines, comprising: receiving video input data representing a plurality of low resolution video input frames; storing a plurality of said lower resolution video input frames at a first clock rate; combining corresponding lines of selected ones of said plurality of stored frames to form a single horizontal line of video data; outputting each of said formed single horizontal lines at a second clock rate substantially greater than said first clock rate thereby producing high resolution video output frames from said formed horizontal lines having a substantially higher resolution than the horizontal lines of said low resolution input frames; and displaying a single frame of video data from a plurality of said formed single horizontal lines.

Claim 5

A method of converting low resolution computer video output data signals to high resolution video output data signals representing high resolution video frames, comprising: generating a plural phase input clock signal; generating a horizontal and vertical synchronous valid signal in response to the low resolution computer video output data signals representing a plurality of low resolution video frame having a plurality of horizontal lines, each of said lines comprising a first number of pixels; storing the data from a plurality of low resolution video frames in a pre-selected arrangement in a frame buffer at a rate corresponding to the plural phase clock signal; combining similar horizontal lines of low resolution video data corresponding to selected ones of said plurality of stored frames to form a single horizontal line of video data having a second number of pixels equal to the sum of the first number of pixels from each of said combined lines; and reading out each of said formed single horizontal lines at a rate greater than said input clock rate thereby producing high resolution video output data signals having a substantially higher resolution than said ow resolution video input signals.

Claim 6

A method of converting low resolution computer video output data signals to high resolution video output data signals representing high resolution video frames, comprising: generating a plural phase input clock signal; generating a horizontal and vertical synchronous valid signal in response to the low resolution computer video output data signals representing a plurality of low resolution video frame having a plurality of horizontal lines, each of said lines comprising a first number of pixels; storing the data from a plurality of low resolution video frames in a pre-selected arrangement in a frame buffer at a rate corresponding to the plural phase clock signal; combining similar horizontal lines of low resolution video data corresponding to selected ones of said plurality of stored frames to form a single horizontal line of video data having a second number of pixels equal to the sum of the first number of pixels from each of said combined lines; and reading out each of said formed single horizontal lines at a rate greater than said input clock rate thereby producing high resolution video output data signals having a substantially higher resolution than said ow resolution video input signals.

Claim 7

A system for generating a high resolution computer video display from a low resolution video computer output, comprising: input means including first clock means for generating a plural phase clock signal and means for generating horizontal and vertical synchronous valid signals in response to horizontal and vertical synchronous signals from a plurality of low resolution computer video output frames, each of said frames having a plurality of horizontal lines comprising control data and video image data; beam counter means operatively coupled to said input means for detecting the scan position for each of said lines of control data and video image data from said input means; input address generating means responsive to said horizontal and vertical valid signals for generating storage addresses for said lines of video image data; buffer means governed by said generated storage addresses, for storing each of said lines of video image data in a selected arrangement, each of said lines of video image data having a first number of pixels corresponding to each of said plurality of low resolution frames; transfer means for transferring said lines of video image data to said frame buffer means; output means address generating means for determining the sequence of read-out of said lines of video image data from said buffer means; means for multiplexing said generated input addresses and said generated output addresses; second clock means for generating output clock signals having a greater repetition rate than said plural phase clock signal from said first clock means; and output means including timing means, responsive to said output clock signals, for generating output video signals for each line of a single high resolution video display frame having a resolution approximately equal to the total of said first number of pixels in each of a plurality of corresponding lines of selected ones of the plurality of low resolution frames.

Claim 8

A system for generating a high resolution computer video display from a low resolution video computer output, comprising: input means including first clock means for generating a plural phase clock signal and means for generating horizontal and vertical synchronous valid signals in response to horizontal and vertical synchronous signals from a plurality of low resolution computer video output frames, each of said frames having a plurality of horizontal lines comprising control data and video image data; beam counter means operatively coupled to said input means for detecting the scan position for each of said lines of control data and video image data from said input means; input address generating means responsive to said horizontal and vertical valid signals for generating storage addresses for said lines of video image data; buffer means governed by said generated storage addresses, for storing each of said lines of video image data in a selected arrangement, each of said lines of video image data having a first number of pixels corresponding to each of said plurality of low resolution frames; transfer means for transferring said lines of video image data to said frame buffer means; output means address generating means for determining the sequence of read-out of said lines of video image data from said buffer means; means for multiplexing said generated input addresses and said generated output addresses; second clock means for generating output clock signals having a greater repetition rate than said plural phase clock signal from said first clock means; and output means including timing means, responsive to said output clock signals, for generating output video signals for each line of a single high resolution video display frame having a resolution approximately equal to the total of said first number of pixels in each of a plurality of corresponding lines of selected ones of the plurality of low resolution frames.