Patent US4851718A successfully refreshed from Google Patents.
US4851718A
Expired / Lapsed
US
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Active filter type signal adjusting circuit
Assignee: Toshiba Corp
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Filing: 1988-09-02
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Granted: 1989-07-25
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Expires: 2008-09-02
Abstract
Abstract A first operational amplifier differentially operates a signal to be adjusted input by an input unit and an adjusted signal output by an output unit. A second operational amplifier differentially operates a first output from the first operational amplifier and the adjusted signal. A buffer supplies a second output from the second operational amplifier to the output unit as the adjusted signal. A first adder obtains a sum component of a first signal obtained by multiplying a first variable m with the signal to be adjusted and a second signal obtained by multiplying a second variable 1-n with the adjusted signal. A first capacitor superposes the sum component of the first and second signals on the first output to supply a superposed signal to the second operational amplifier. A second adder obtains the signal to be adjusted or a component obtained by multiplying the first variable m with the signal to be adjusted as a third signal. A second capacitor superposes the third signal on the second output to supply a superposed signal to the buffer. The first and second variables m and 1-n are selected as desirable values in an adjusting mode and are respectively set to be m=n=1 (where 0≦n and m≦1) in a non-adjusting mode.
Inventors
- 👤 Hideyuki Hagino
- 👤 Takahiro Kusano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:15
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/14; H04N5/20; H04N5/205; H03; H03H; H03H11/00; H03H11/02; H03H11/04; H03H11/0422; H03H11/0472; H03H2210/00; H03H2210/01; H03H2210/017
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
285 words
An active filter type signal adjusting circuit comprising: input means for inputting a signal to be adjusted; output means for outputting an adjusted signal; first operational amplifier means for differentially operating the signal to be adjusted input by said input means and the adjusted signal output by said output means; second operational amplifier means for differentially operating an output from said first operational amplifier means and the adjusted signal output by said output means; buffer amplifier means for supplying an output from said second operational amplifier means to said output means as the adjusted signal; first adding means for obtaining a sum component of a first signal obtained by multiplying a first variable m with the signal to be adjusted input by said input means and a second signal obtained by multiplying a second variable 1-n with the adjusted signal output by said output means; first capacitor means for superposing the sum component of the first and second signals obtained by said first adding means on the output from said first operational amplifier means to supply a superposed signal to said second operational amplifier means; second adding means for obtaining as a third signal, the signal to be adjusted input by said input means or a component obtained by multiplying the first variable m with the signal to be adjusted; and second capacitor means for superposing the third signal obtained by said second adding means on the output from said second operational amplifier means to supply a superposed signal to said buffer amplifier means, the first and second variables being selected as desirable values m and 1-n in an adjusting mode, and being respectively set to m=n=1 (where 0≦n and m=1) in a non-adjusting mode.
Claim 2
Dependent Claim
285 words
An active filter type signal adjusting circuit comprising: input means for inputting a signal to be adjusted; output means for outputting an adjusted signal; first operational amplifier means for differentially operating the signal to be adjusted input by said input means and the adjusted signal output by said output means; second operational amplifier means for differentially operating an output from said first operational amplifier means and the adjusted signal output by said output means; buffer amplifier means for supplying an output from said second operational amplifier means to said output means as the adjusted signal; first adding means for obtaining a sum component of a first signal obtained by multiplying a first variable m with the signal to be adjusted input by said input means and a second signal obtained by multiplying a second variable 1-n with the adjusted signal output by said output means; first capacitor means for superposing the sum component of the first and second signals obtained by said first adding means on the output from said first operational amplifier means to supply a superposed signal to said second operational amplifier means; second adding means for obtaining as a third signal, the signal to be adjusted input by said input means or a component obtained by multiplying the first variable m with the signal to be adjusted; and second capacitor means for superposing the third signal obtained by said second adding means on the output from said second operational amplifier means to supply a superposed signal to said buffer amplifier means, the first and second variables being selected as desirable values m and 1-n in an adjusting mode, and being respectively set to m=n=1 (where 0≦n and m=1) in a non-adjusting mode.
Claim 3
Dependent Claim
87 words
A circuit according to claim 1, wherein said first adding means comprises a first variable gain amplifier for multiplying m serving as the first variable with the signal to be adjusted input by said input means to output the first signal, a second variable gain amplifier for multiplying (1-n) serving as the second variable with the adjusted signal output by said output means to output the second signal, and an adder for adding the first and second signals output by said first and second variable gain amplifiers.
Claim 4
Dependent Claim
30 words
A circuit according to claim 2, wherein the first and second signals output by said first and second variable gain amplifiers are supplied to said adder through corresponding buffer circuits.
Claim 5
Dependent Claim
40 words
A circuit according to claim 1, wherein said second adding means includes a variable gain amplifier for multiplying m serving as the first variable with the signal to be adjusted input by said input means to output the third signal.
Claim 6
Dependent Claim
38 words
A circuit according to claim 2, wherein an output from said first variable gain amplifier is commonly used as the first signal obtained by said first adding means and the third signal obtained by said second adding means.
Claim 7
Dependent Claim
27 words
A circuit according to claim 1, wherein said second adding means directly transfers the signal to be adjusted input by said input means as the third signal.
Claim 8
Dependent Claim
284 words
An active filter type signal adjusting circuit comprising: input means for inputting a signal to be adjusted; output means for outputting an adjusted signal; first operational amplifier means for differentially operating the signal to be adjusted input by said input means and the adjusted signal output by said output means; second operational amplifier means for differentially operating an output from said first operational amplifier means and the adjusted signal output by said output means; buffer amplifier means for supplying an output from said second operational amplifier means to said output means as the adjusted signal; first and second adding means each for obtaining a first signal obtained by multiplying a first variable m with the signal to be adjusted input by said input means and a second signal obtained by multiplying a second variable 1-n with the adjusted signal output by said output means; first and second capacitor means for superposing the first and second signals obtained by said first and second adding means on the output from said first operational amplifier means to supply a superposed signal to said second operational amplifier means; third adding means for obtaining, as a third signal, the signal to be adjusted input by said input means or a component obtained by multiplying the first variable m with the signal to be adjusted; and third capacitor means for superposing the third signal obtained by said third adding means on the output from said second operational amplifier means to supply a superposed signal to said buffer amplifier means, the first and second variables m and 1-n being selected as desirable values in an adjusting mode and being respectively set to m=n (where 0≦m and n≦1) in a non-adjusting mode.
Claim 9
Dependent Claim
284 words
An active filter type signal adjusting circuit comprising: input means for inputting a signal to be adjusted; output means for outputting an adjusted signal; first operational amplifier means for differentially operating the signal to be adjusted input by said input means and the adjusted signal output by said output means; second operational amplifier means for differentially operating an output from said first operational amplifier means and the adjusted signal output by said output means; buffer amplifier means for supplying an output from said second operational amplifier means to said output means as the adjusted signal; first and second adding means each for obtaining a first signal obtained by multiplying a first variable m with the signal to be adjusted input by said input means and a second signal obtained by multiplying a second variable 1-n with the adjusted signal output by said output means; first and second capacitor means for superposing the first and second signals obtained by said first and second adding means on the output from said first operational amplifier means to supply a superposed signal to said second operational amplifier means; third adding means for obtaining, as a third signal, the signal to be adjusted input by said input means or a component obtained by multiplying the first variable m with the signal to be adjusted; and third capacitor means for superposing the third signal obtained by said third adding means on the output from said second operational amplifier means to supply a superposed signal to said buffer amplifier means, the first and second variables m and 1-n being selected as desirable values in an adjusting mode and being respectively set to m=n (where 0≦m and n≦1) in a non-adjusting mode.
Claim 10
Dependent Claim
74 words
A circuit according to claim 7, wherein said first adding means comprising a first variable gain amplifier for multiplying m serving as the first variable with the signal to be adjusted input by said input means to output the first signal, and said second adding means comprises a second variable gain amplifier for multiplying (1-n) serving as the second variable with the adjusted signal output by said output means to output the second signal.
Claim 11
Dependent Claim
40 words
A circuit according to claim 7, wherein said third adding means comprises a variable gain amplifier for multiplying m serving as the first variable with the signal to be adjusted input by said input means to output the third signal.
Claim 12
Dependent Claim
38 words
A circuit according to claim 8, wherein an output from said first variable gain amplifier is commonly used as the first signal obtained by said first adding means and the third signal obtained by said third adding means.
Claim 13
Dependent Claim
27 words
A circuit according to claim 7, wherein said third adding means directly transfers the signal to be adjusted input by said input means as the third signal.
References Cited (Backward Citations)
US3978409A
Cited
US4063450A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |