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Patent US4851713A successfully refreshed from Google Patents.
US4851713A
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Fast CMOS NAND gate circuit
Assignee: Verizon Laboratories Inc
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Filing: 1988-03-10
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Granted: 1989-07-25
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Expires: 2008-03-10
Abstract
Abstract An n-input CMOS NAND-gate having n pMOS transistors connected in parallel with their inputs connected to different input terminals and their outputs connected to a common output terminal. First and second sets of n nMOS transistors are each connected in series between the output terminal and ground. The inputs of the first set of nMOS transistors are connected to the input terminals in order, and the inputs of the second set of nMOS transistors are connected to the input terminals in the reverse order.
Inventors
- 👤 Sywe-Neng Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:39
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
376 words
A logic circuit comprising a plurality of input terminals for receiving input signals at a first or a second logic level; an output terminal; a like plurality of transistors of a first conductivity type connected in parallel between a source of operating potential and said output terminal, and each having an input connected to one of said input terminals; a first set of a like plurality of transistors of a second conductivity type connected in series between said output terminal and a point of reference potential, each having an input connected to one of said input terminals; and a second set of a like plurality of transistors of said second conductivity type connected in series between said output terminal and said point of reference potential, each having an input connected to one of said input terminals such that each transistor in said first set is paired with a transistor in said second set having a like position in said series and both are connected to the same one of said input terminals; wherein the last transistor in said series of transistors of said first set is connected to ground; and wherein the first transistor in said series of transistors of said second set is connected to ground; wherein said first conductivity type is opposite to said second conductivity type; and wherein each transistor of said first conductivity type is in a conducting condition in response to an input signal of said first logic level at its input and is in a nonconducting condition in response to an input signal of said second logic level at its input; and each transistor of said second conductivity type is in a nonconducting condition in response to an output signal of said first logic level at its input and is in a conducting condition in response to an input signal of said second logic level at its input; whereby said output terminal is at the potential of the source of operating potential when input signals of the first logic level are present at one or more of the input terminals, and said output terminal is at the potential of the point of reference potential when input signals of the second logic level are present at all of the input terminals.
Claim 2
Dependent Claim
376 words
A logic circuit comprising a plurality of input terminals for receiving input signals at a first or a second logic level; an output terminal; a like plurality of transistors of a first conductivity type connected in parallel between a source of operating potential and said output terminal, and each having an input connected to one of said input terminals; a first set of a like plurality of transistors of a second conductivity type connected in series between said output terminal and a point of reference potential, each having an input connected to one of said input terminals; and a second set of a like plurality of transistors of said second conductivity type connected in series between said output terminal and said point of reference potential, each having an input connected to one of said input terminals such that each transistor in said first set is paired with a transistor in said second set having a like position in said series and both are connected to the same one of said input terminals; wherein the last transistor in said series of transistors of said first set is connected to ground; and wherein the first transistor in said series of transistors of said second set is connected to ground; wherein said first conductivity type is opposite to said second conductivity type; and wherein each transistor of said first conductivity type is in a conducting condition in response to an input signal of said first logic level at its input and is in a nonconducting condition in response to an input signal of said second logic level at its input; and each transistor of said second conductivity type is in a nonconducting condition in response to an output signal of said first logic level at its input and is in a conducting condition in response to an input signal of said second logic level at its input; whereby said output terminal is at the potential of the source of operating potential when input signals of the first logic level are present at one or more of the input terminals, and said output terminal is at the potential of the point of reference potential when input signals of the second logic level are present at all of the input terminals.
Claim 3
Dependent Claim
28 words
A logic circuit in accordance with claim 1 wherein said transistors of said first conductivity type are P-type; and said transistors of said second conductivity type are N-type.
Claim 4
Dependent Claim
45 words
A logic circuit in accordance with claim 1 wherein said transistors of the first conductivity type are pMOS transistors; said transistors of the second conductivity type are nMOS transistors; and said source of operating potential is positive with respect to said point of reference potential.
References Cited (Backward Citations)
US4736117A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |