US4849998A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Rate synchronized symbol timing recovery for variable rate data transmission systems
Assignee: Comsat Corp
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Filing: 1988-06-03
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Granted: 1989-07-18
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Expires: 2008-06-03
Abstract
Abstract A symbol timing recovery circuit with a clock synchronization loop for variable rate data signals utilizes a frequency synthesizer for setting the frequency of the recovered clock signal. The received data signal, representing the modulating waveform of a transmitted modulated wareform, is estimated by passage through a data filter and sampling comparator sampled by the recovered clock. The received data signal is also delayed and multiplied by the time derivative of the estimated data signal to produce an error signal representing the difference between the incoming data rate and the output of a narrow pull range voltage controlled oscillator, VCO. The error signal is input to the VCO to correct the VCO output. A programmable frequency synthesizer provides timing signals having a range of the symbol rate divided by n. The VCO output is mixed with the frequency synthesizer output and the sum signals removed by a low pass signal to produce the difference signals which will correspond to the clock signal of the data signal.
Inventors
- 👤 John J. Poklemba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:32
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0054; H04L7/02; H04L7/033; H04L7/0334
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A symbol timing recovery circuit for variable rate data signals comprising: means for producing an estimate of a data signal; first mixing means for mixing a signal representative of the data signals and a signal representative of the estimate of the data signals to produce an error signal representing the difference between the data signal rate and the output of a voltage controlled oscillator; a voltage controlled oscillator responsive to said error signal; a frequency synthesizer for producing selected ones of a plurality of timing signals within a range of frequencies corresponding to the frequency range of the variable rate data signals; and second mixing means for mixing the output from the voltage controlled oscillator and the selected timing signal from the frequency synthesizer to produce a signal at the rate of the data signal as the recovered clock.
Claim 2
Dependent Claim
139 words
A symbol timing recovery circuit for variable rate data signals comprising: means for producing an estimate of a data signal; first mixing means for mixing a signal representative of the data signals and a signal representative of the estimate of the data signals to produce an error signal representing the difference between the data signal rate and the output of a voltage controlled oscillator; a voltage controlled oscillator responsive to said error signal; a frequency synthesizer for producing selected ones of a plurality of timing signals within a range of frequencies corresponding to the frequency range of the variable rate data signals; and second mixing means for mixing the output from the voltage controlled oscillator and the selected timing signal from the frequency synthesizer to produce a signal at the rate of the data signal as the recovered clock.
Claim 3
Dependent Claim
42 words
A symbol timing recovery circuit for variable rate data signals as claimed in claim 1, further including a low pass filter to eliminate from the output of said second mixing means signals other than those at the rate of said data signals.
Claim 4
Dependent Claim
56 words
A symbol timing recovery circuit for variable rate data signals as claimed in claim 2 wherein said frequency synthesizer is programmable in divisions R s '/n, where R s ' is the highest expected data rate and n is a clock rate range, and said voltage controlled oscillator has a frequency (n+1)/n of R s '.
Claim 5
Dependent Claim
32 words
A symbol timing recovery circuit for variable rate data signals as claimed in claim 3 further including a frequency divider network for selectively frequency dividing the output from said low pass filter.
Claim 6
Dependent Claim
28 words
A symbol timing recovery circuit for variable rate data signals as claimed in claim 1 wherein said voltage controlled oscillator is a narrow pull range voltage controlled oscillator.
Claim 7
Dependent Claim
24 words
A symbol timing recovery circuit for variable rate data signals as claimed in claim 5 wherein said voltage controlled oscillator is a crystal oscillator.
Claim 8
Dependent Claim
142 words
A symbol timing recovery circuit for variable rate data signal comprising: means for producing an estimate of a data signal, said estimate producing means being responsive to a reproduced clock signal of the data signal; a narrow pull range voltage controlled oscillator generating a reproduced clock signal at the rate (n+1)/n)R s 'where R s ' is the highest data rate of said variable rate data signals; error signal means for producing an error signal representing a difference between an input data signal and its estimate, said error signal controlling said voltage controlled oscillator; frequency synthesizer means selectively generating frequencies within the range R s ' /n to R s ', where n is a clock rate range; and means coupled to the outputs of said voltage controlled oscillator and said frequency synthesizer for reproducing the clock signal of the data signal.
Claim 9
Dependent Claim
142 words
A symbol timing recovery circuit for variable rate data signal comprising: means for producing an estimate of a data signal, said estimate producing means being responsive to a reproduced clock signal of the data signal; a narrow pull range voltage controlled oscillator generating a reproduced clock signal at the rate (n+1)/n)R s 'where R s ' is the highest data rate of said variable rate data signals; error signal means for producing an error signal representing a difference between an input data signal and its estimate, said error signal controlling said voltage controlled oscillator; frequency synthesizer means selectively generating frequencies within the range R s ' /n to R s ', where n is a clock rate range; and means coupled to the outputs of said voltage controlled oscillator and said frequency synthesizer for reproducing the clock signal of the data signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |