Patent US4849993A successfully refreshed from Google Patents.
US4849993A
Expired / Lapsed
US
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Clock holdover circuit
Assignee: JPMorgan Chase Bank NA
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Filing: 1987-12-10
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Granted: 1989-07-18
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Expires: 2007-12-10
Abstract
Abstract The present invention provides a clock holdover circuit which will provide a replacement clock signal within predetermined parameters independently of time and temperature variations. The circuit of the present invention has only a single component which is time and temperature dependent. By selecting the components parameters to be within the desired tolerances, the accuracy of the circuit is maintained. In the present invention, digital circuitry is combined with an accurate local crystal frequency source to provide a replacement clock signal. The present invention allows phase consistency upon loss of a reference clock signal as well as on return of the reference clock signal. A reference clock signal is phase locked to a VCO to produce a desired output. The frequency of the output is compared to a local frequency standard to generate an offset frequency used to control a frequency synthesizer. The offset frequency is digitally stored. Upon loss of the reference clock signal, the stored offset frequency is used to drive the frequency synthesizer along with the local frequency standard so as to provide an acceptable replacement clock signal. The frequency comparator, storage, and synthesizer are all digital so as to be time and temperature independent. The local frequency standard is crystal based having known time and temperature tolerances. By choosing a local frequency standard having tolerances within a predetermined range, an acceptable clock holdover signal may be provided indefinitely. The replacement clock signal is phase compared to the reference clock signal so that no loss of phase occurs upon reference loss.
Inventors
- 👤 Steven Johnson
- 👤 Toney Warren
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:25
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H03L7/143; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083; H03L7/145
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
310 words
A clock holdover circuit comprising: receiving means for receiving a first clock signal having a first frequency and a first phase, said receiving means for detecting the presence and absence of said first clock signal and the accuracy of said first clock signal; first phase comparing means coupled to said first clock signal and through a switch means to a first frequency generating means, said phase comparing means outputting a first output signal to said first frequency generating means, said first frequency generating means outputting a second output signal to said first phase comparing means in a feedback loop; second frequency generating means outputting a third output signal having a second frequency and phase coupled to mixing means, said second output signal coupled to said mixing means, said mixing means outputting a fourth output signal representing a difference in frequency between said second and third output signals; frequency synthesizing means coupled to said second frequency generating means, said frequency synthesizing means outputting a fifth output signal representing a nominal difference between said second and third output signals; frequency comparing means coupled to said fourth and fifth output signals and outputting a sixth output signal representing a difference between said fourth and fifth output signals; storage means coupled to said sixth output signal and a first control signal, for storing said sixth output signal, said storge means coupled to said frequency synthesizing means; second phase comparing means coupled to said fourth and fifth output signals, said second phase comparing means outputting a seventh output signal; said receiving means outputting said first control signal to couple a stored value of said sixth output signal to said first frequency synthesizing means and outputting a second control signal to couple said switch means to said seventh output signal when said first clock signal is absent and when said first clock signal is not accurate.
Claim 2
Dependent Claim
310 words
A clock holdover circuit comprising: receiving means for receiving a first clock signal having a first frequency and a first phase, said receiving means for detecting the presence and absence of said first clock signal and the accuracy of said first clock signal; first phase comparing means coupled to said first clock signal and through a switch means to a first frequency generating means, said phase comparing means outputting a first output signal to said first frequency generating means, said first frequency generating means outputting a second output signal to said first phase comparing means in a feedback loop; second frequency generating means outputting a third output signal having a second frequency and phase coupled to mixing means, said second output signal coupled to said mixing means, said mixing means outputting a fourth output signal representing a difference in frequency between said second and third output signals; frequency synthesizing means coupled to said second frequency generating means, said frequency synthesizing means outputting a fifth output signal representing a nominal difference between said second and third output signals; frequency comparing means coupled to said fourth and fifth output signals and outputting a sixth output signal representing a difference between said fourth and fifth output signals; storage means coupled to said sixth output signal and a first control signal, for storing said sixth output signal, said storge means coupled to said frequency synthesizing means; second phase comparing means coupled to said fourth and fifth output signals, said second phase comparing means outputting a seventh output signal; said receiving means outputting said first control signal to couple a stored value of said sixth output signal to said first frequency synthesizing means and outputting a second control signal to couple said switch means to said seventh output signal when said first clock signal is absent and when said first clock signal is not accurate.
Claim 3
Dependent Claim
16 words
The circuit of claim 1 wherein said first frequency generating means comprises a voltage controlled oscillator.
Claim 4
Dependent Claim
17 words
The circuit of claim 1 wherein said second frequency generating means comprises a crystal base frequency reference.
Claim 5
Dependent Claim
15 words
The circuit of claim 1 wherein said freuqency comparing means comprises a digital frequency comparator.
Claim 6
Dependent Claim
15 words
The circuit of claim 1 wherein said frequency synthesizing means comprises a digital frequency synthesizer.
Claim 7
Dependent Claim
117 words
A clock holdover circuit comprising: a first frequency generating means phase locked to an input signal and producing a first output signal at a desired frequency; a first comparing means coupled to a local frequency standard and to said first output signal for generating a second output signal, said second output signal being an offset between said local frequency standard and said first output signal; storage means coupled to said first comparing means for storing said second output signal; a second frequency generating means coupled to said storage means, said second frequency generating means driven by said second output signal to produce a third output signal at said desired frequency when said input signal is not available.-
Claim 8
Dependent Claim
117 words
A clock holdover circuit comprising: a first frequency generating means phase locked to an input signal and producing a first output signal at a desired frequency; a first comparing means coupled to a local frequency standard and to said first output signal for generating a second output signal, said second output signal being an offset between said local frequency standard and said first output signal; storage means coupled to said first comparing means for storing said second output signal; a second frequency generating means coupled to said storage means, said second frequency generating means driven by said second output signal to produce a third output signal at said desired frequency when said input signal is not available.-
Claim 9
Dependent Claim
16 words
The circuit of claim 6 wherein said first frequency generating means comprises a voltage controlled oscillator.
Claim 10
Dependent Claim
15 words
The circuit of claim 6 wherein said local frequency standard comprises a crystal based oscillator.
Claim 11
Dependent Claim
16 words
The circuit of claim 6 wherein said second frequency generating means comprises a digital frequency synthesizer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |