Event counting prescaler

Claim 1

An apparatus for non-intrusively counting the number of times at least one selected event code appears on a bus of a central processing unit, the apparatus comprising: storage means having an address port, a data out port and a data in port, said storage means of storing an event count corresponding to each of said at least one selected event code with each of said at least one selected event code corresponding to a different address of the storage means; a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to the address port of the storage means, said third address bus for addressing said storage means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; and incrementing means coupled to receive the stored event count from the data out port of the storage means for incrementing the stored event count for each of said at least one selected event code when each event occurs and coupling that incremented event count to the data in port of the storage means for storage as the new event count.

Claim 2

An apparatus for non-intrusively counting the number of times at least one selected event code appears on a bus of a central processing unit, the apparatus comprising: storage means having an address port, a data out port and a data in port, said storage means of storing an event count corresponding to each of said at least one selected event code with each of said at least one selected event code corresponding to a different address of the storage means; a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to the address port of the storage means, said third address bus for addressing said storage means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; and incrementing means coupled to receive the stored event count from the data out port of the storage means for incrementing the stored event count for each of said at least one selected event code when each event occurs and coupling that incremented event count to the data in port of the storage means for storage as the new event count.

Claim 6

An apparatus for non-intrusively counting the number of times at least one selected event code appears on a bus of a central processing unit, the apparatus comprising: random access memory means for storing an event count at an address determined by the event code, said memory means being addressed by said event code when said event occurs, said memory means thereupon outputting said event count; a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to an address port of the memory means, said third address bus for addressing said memory means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; latch means coupled to receive said outputted event count from the memory means for latching said outputted event count on assertion of a latch clock pulse, said latch clock pulse being asserted after said event count is outputted by said memory means; adder means, having one input port for receiving the latched event count from the latch means and having another input port for receiving a fixed increment number, said adder means generates an incremented event count as the sum of the latched event count and the fixed increment number; and writing means for writing said incremented event count from the adder means back into said memory means at the memory address corresponding to the counted event code.

Claim 7

An apparatus for non-intrusively counting the number of times at least one selected event code appears on a bus of a central processing unit, the apparatus comprising: random access memory means for storing an event count at an address determined by the event code, said memory means being addressed by said event code when said event occurs, said memory means thereupon outputting said event count; a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to an address port of the memory means, said third address bus for addressing said memory means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; latch means coupled to receive said outputted event count from the memory means for latching said outputted event count on assertion of a latch clock pulse, said latch clock pulse being asserted after said event count is outputted by said memory means; adder means, having one input port for receiving the latched event count from the latch means and having another input port for receiving a fixed increment number, said adder means generates an incremented event count as the sum of the latched event count and the fixed increment number; and writing means for writing said incremented event count from the adder means back into said memory means at the memory address corresponding to the counted event code.

Claim 8

An apparatus for non-intrusively counting the occurrences of a plurality of selected event codes on a bus of a central processing unit, each event code being unique, the apparatus comprising: random access memory means having an address port, an input port and an output port, said memory means stores event counts at addresses determined by the event codes; address means coupled to the address port of the memory means for selectively addressing said memory means by one of said event codes when a corresponding one of said plurality of event codes occurs, said memory means subsequently outputting said corresponding event count on its output port, said address means includes: a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to the address port of the memory means, said third address bus for addressing said memory means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; and incrementing means coupled to the output port of the memory means for incrementing the outputted event count subsequently, said incremented event count being written back into said input port of the memory means at the address corresponding to event code last outputted from said memory means.

Claim 9

An apparatus for non-intrusively counting the occurrences of a plurality of selected event codes on a bus of a central processing unit, each event code being unique, the apparatus comprising: random access memory means having an address port, an input port and an output port, said memory means stores event counts at addresses determined by the event codes; address means coupled to the address port of the memory means for selectively addressing said memory means by one of said event codes when a corresponding one of said plurality of event codes occurs, said memory means subsequently outputting said corresponding event count on its output port, said address means includes: a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to the address port of the memory means, said third address bus for addressing said memory means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; and incrementing means coupled to the output port of the memory means for incrementing the outputted event count subsequently, said incremented event count being written back into said input port of the memory means at the address corresponding to event code last outputted from said memory means.

Claim 11

An apparatus for non-intrusively counting the occurrences of a plurality of selected event codes on a bus of a central processing unit, each event code being unique, the apparatus comprising: random access memory means having an address port and an output port, said memory means stores event counts at addresses corresponding to the event codes; a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to the address bus coupled to the address port of the memory means, said third address bus for addressing said memory means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; an adder having one input port for receiving the outputted event count from the output port of the memory means and having another input port for receiving a fixed increment number, said adder generating said incremented event count as the sum of the outputted event count and the fixed increment number; and buffer means for storing event codes appearing on said second address bus when said adder asserts an overflow signal.

Claim 12

An apparatus for non-intrusively counting the occurrences of a plurality of selected event codes on a bus of a central processing unit, each event code being unique, the apparatus comprising: random access memory means having an address port and an output port, said memory means stores event counts at addresses corresponding to the event codes; a first address bus for carrying an address which is generated independently of any event code; a second address bus for carrying event codes; a third address bus coupled to the address bus coupled to the address port of the memory means, said third address bus for addressing said memory means; multiplexer means for selectively connecting either said first or second address busses to said third address bus; an adder having one input port for receiving the outputted event count from the output port of the memory means and having another input port for receiving a fixed increment number, said adder generating said incremented event count as the sum of the outputted event count and the fixed increment number; and buffer means for storing event codes appearing on said second address bus when said adder asserts an overflow signal.

Claim 13

An apparatus for non-intrusively counting the occurrences of a plurality of selected event codes on a bus of a central processing unit, each event code being unique, the apparatus comprising: random access memory means having an address port, an input port and an output port, said memory means stores event counts at addresses determined by the event codes; address means coupled to the address port of the memory means for selectively addressing said memory means by one of said event codes when a corresponding one of said plurality of event codes occurs, said memory means subsequently outputting said corresponding event count on its output port; incrementing means coupled to the output port of the memory means for incrementing the outputted event count, subsequently, said incremented event count being written back into said input port of the memory means at the address corresponding to event code last outputted from said memory means; and a buffer coupled to said incrementing means and to the address port of said random access memory means for storing said event codes whenever said incrementing means asserts an overflow signal.

Claim 14

An apparatus for non-intrusively counting the occurrences of a plurality of selected event codes on a bus of a central processing unit, each event code being unique, the apparatus comprising: random access memory means having an address port, an input port and an output port, said memory means stores event counts at addresses determined by the event codes; address means coupled to the address port of the memory means for selectively addressing said memory means by one of said event codes when a corresponding one of said plurality of event codes occurs, said memory means subsequently outputting said corresponding event count on its output port; incrementing means coupled to the output port of the memory means for incrementing the outputted event count, subsequently, said incremented event count being written back into said input port of the memory means at the address corresponding to event code last outputted from said memory means; and a buffer coupled to said incrementing means and to the address port of said random access memory means for storing said event codes whenever said incrementing means asserts an overflow signal.