Electronic timepiece circuit

Claim 1

An electronic timepiece which comprises a clock pulse oscillator; a timing pulse generator for dividing the frequency of a clock pulse produced by the clock pulse oscillator to issue a timing pulse; an address pulse generator for sending forth address pulses to designate a prescribed address being stored with a time data upon receipt of a timing pulse from the timing pulse generator; a memory circuit formed of a plurality of static random access memory cells arranged in the form of a matrix represented by a number of time data by a number of bits required to denote the code of each time data, and, when a word-selecting line connected to a memory cell is supplied with an address pulse designating said memory cell, sending forth a time data through a data line of the designated memory cell; a display device for displaying a time data head out from the memory circuit; a carry-judging circuit for deciding whether a time data issued from the memory cell should be carried up to an immediately following higher unit time level and generating a carry-instructing signal; a reset-judging circuit for generating a reset-judging circuit for generating a reset-instructing signal where carry is required, to clear the carried time data; a first delay circuit for holding a carry-instructing signal delivered from the carry-judging circuit until a time data being carried is received; a second delay circuit for holding a reset-instructing signal until a time data being cleared is received; an adder for adding a carry signal supplied from the first delay circuit and a minimum unit time signal to a time data read out from the memory circuit; and a correction circuit for correcting a time data delivered from said adder upon receipt of a reset signal from the second display circuit.