Method and apparatus for circuit units

Claim 3

The method in claim 1 wherein the address generation signal modification step comprises interrupting the transmission of the address generation signal along the path in such a manner that the interruption is sequentially effected at successive coupling points along the path.

Claim 4

The method in claim 1 further comprising the steps of arranging each circuit unit to modify the address generation signal at regular intervals or at intervals dependent on the nature of the address generation signal, detecting, at each circuit unit whether a previous circuit unit nearer to the end of the path from which the address generation signal is transmitted has modified the address generation signal, and preventing each circuit unit which has detected that no previous unit has modified the address generation signal from subsequently modifying the address generation signal.

Claim 5

The method in claim 1 wherein the address generation signal comprises a plurality of pulses or sets of pulses.

Claim 6

The method of claim 3 in which the address generation signal comprises a carrier signal modulated by a signal which includes a plurality of pulses or sets of pulses.

Claim 7

The method in claim 4 in which each circuit unit includes an address generator characterised in that the address generator of each unit is arranged to count the pulses or sets of pulses present at its coupling point either until or from a time dependent on the instant when the circuit unit has detected that no previous circuit unit has modified the address generation signal, the address allocated to each circuit unit being dependent on the count contained in its address generator.

Claim 8

The method in claim 1 wherein: the address generation signal comprises one or more level transitions or one or more pulses, each circuit unit modifies the address generation signal by adding one or more level transitions or pulses to the address generation signal arriving at the coupling point to which that circuit unit is coupled, and each circuit unit includes an address generator which counts the number of level transitions or pulses received at its coupling point and adopts an address dependent on the number counted.

Claim 9

The method in claim 7 wherein the level transitions or pulses modulate a carrier signal, and each circuit unit demodulates the signal received at its coupling point, modifies the demodulated signal by adding one or more level transitions or pulses, re-modulates the modified signal and applies the remodulated signal to the path, and each circuit unit address generator counts the number of level transitions or pulses in the demodulated signal and adopts an address dependent on the number counted.

Claim 11

A network for generating and allocating a unique address for each of a plurality of circuit units comprising: a plurality of circuit units coupled to a single path at individual spaced, coupling points along its length, and a control circuit for transmitting an address generation signal along the path from one end thereof, from which address generation signal each circuit unit derives for itself a unique address, and wherein each circuit unit comprises; and address generator, means for modifying the address generation signal at its coupling point, monitoring means for determining whether a circuit unit having a coupling point nearer to said one end has modified the address generation signal and producing an output signal dependent thereon, means for inhibiting the action of the modifying means in response to the output signal from the monitoring means, and means for controlling the address generator in response to modified and unmodified address generation signals present at its coupling point.

Claim 12

A network for generating and allocating a unique address for each of a plurality of circuit units comprising: a plurality of circuit units coupled to a single path at individual spaced, coupling points along its length, and a control circuit for transmitting an address generation signal along the path from one end thereof, from which address generation signal each circuit unit derives for itself a unique address, and wherein each circuit unit comprises; and address generator, means for modifying the address generation signal at its coupling point, monitoring means for determining whether a circuit unit having a coupling point nearer to said one end has modified the address generation signal and producing an output signal dependent thereon, means for inhibiting the action of the modifying means in response to the output signal from the monitoring means, and means for controlling the address generator in response to modified and unmodified address generation signals present at its coupling point.

Claim 13

The network in claim 10, wherein the address generation signal comprises a plurality of pulses or sets of pulses or a carrier signal modulated by said pulses or sets of pulses, and the modifying means is operative for time intervals which start a given time after commencement of each pulse or set of pulses and which end before commencement of the next pulse or set of pulses.

Claim 14

The network in claim 11, wherein the address generation signal comprises a plurality of pulse pairs.

Claim 15

The network in claim 10 wherein the modifying means comprises means for interrupting passage of the address generation signal along the path.

Claim 16

The network in claim 11, wherein the address generator in each circuit unit comprises a binary counter which is incremented or decremented by the pulses or sets of pulses of the address generation signal until or from an instant dependent on the output signal from the monitoring means.

Claim 17

The network in claim 13 wherein the address generator of each circuit unit is coupled to the path at a first point nearer to the control circuit than a second on the path at which the modifying means of that circuit unit is connected.

Claim 18

The circuit unit in claim 15, wherein a delay element is coupled in the path between the first and second points.

Claim 19

The network in claim 10 wherein the address generation signal comprises a plurality of pulse pairs and the modifying means comprise means for interrupting passage of the address generation signal along the path, said interrupting means being effective to interrupt the path for a period which starts between the end of the first and the start of the second pulse and ends after the end of the second pulse of each pulse pair.

Claim 20

The network in claim 11 wherein the controlling means comprises a bistable circuit set to a desired state in response to a signal from the monitoring means, and means coupling an output of the bistable circuit to the address generator to prevent the address generator from responding to further pulses received from the path.

Claim 21

The network in claim 13 wherein the path is a transmission line.

Claim 22

The network in claim 19, characterised in that the transmission line is an electrical transmission line terminated by its characteristic impedance.

Claim 23

The network in claim 20 wherein said interrupting means comprises means for short circuiting the transmission line.

Claim 24

The network in claim 21, wherein said monitoring means comprises means for detecting a current flowing in the short circuit.

Claim 25

The network in claim 20 wherein said interrupting means comprises means for open circuiting said transmission line.

Claim 26

The network in claim 23, wherein said means for open circuiting said transmission line further comprises means for terminating the open circuited section of the transmission line with its characteristic impedance.

Claim 27

The network in any of claims 10 to 24, wherein the control circuit includes a device to transmit a reset signal along said common path and each circuit unit further comprises means for detecting said reset signal and producing an output signal for resetting the address generator.

Claim 28

A network for generating and allocating a unique address for each of a plurality of circuit units, comprising: a plurality of circuit units coupled to a single path at individual spaced, coupling points along its length, and a control circuit for transmitting an address generation signal along the path from one end thereof, wherein each circuit unit comprise; an address generator, the address generation signal including one or more signal level transitions or pulses or a carrier signal modulated by said one or more signal level transitions or pulses, means for modifying the address generation signal received at its coupling point by adding one or more further level transitions or pulses to the received signal, means for applying the modified signal to the path for transmission along said path to a succeeding coupling point, and means for applying the received signal to the address generator so that the circuit unit generates an address for itself dependent on the number of level transitions or pulses received at its coupling point.

Claim 29

A network for generating and allocating a unique address for each of a plurality of circuit units, comprising: a plurality of circuit units coupled to a single path at individual spaced, coupling points along its length, and a control circuit for transmitting an address generation signal along the path from one end thereof, wherein each circuit unit comprise; an address generator, the address generation signal including one or more signal level transitions or pulses or a carrier signal modulated by said one or more signal level transitions or pulses, means for modifying the address generation signal received at its coupling point by adding one or more further level transitions or pulses to the received signal, means for applying the modified signal to the path for transmission along said path to a succeeding coupling point, and means for applying the received signal to the address generator so that the circuit unit generates an address for itself dependent on the number of level transitions or pulses received at its coupling point.

Claim 30

The network in claim 26, wherein the address generator comprises a binary counter which counts the number of level transitions or pulses received and whose state is adopted as the address of the circuit unit.

Claim 31

The network as claimed in claim 26 wherein the control circuit includes means for transmitting a reset signal and each circuit unit includes detecting means for detecting the reset signal and producing an output signal which is effective to reset the address generator to an initial state.

Claim 32

The network in claim 26, wherein the address generation signal comprises a carrier signal modulated by one or more level transitions or pulses or a plurality of pulses or sets of pulses, and each circuit unit includes a demodulator for demodulating the modulated carrier signal present at its coupling point, means for modifying the demodulated signal, means for remodulating the modified signal, means for applying the remodulated signal to the path for transmission to succeeding circuit units, and means for deriving its address from the demodulated signals.

Claim 33

The network in claim 29, wherein each circuit unit includes a radio receiver and a radio transmitter, each radio transmitter being arranged to transmit a signal only to one receiver and that the single path comprises the transmitters and receivers and paths therebetween.

Claim 34

A circuit unit suitable for use in the network in any of claims 10 to 20 or 28 to 30 comprising an input for connection to said coupling point and an address generator coupled to said input, the state of the address generator being modified in response to address generation signals applied to said input means for modifying the address generation signal applied to said input and output means for applying the modified address generation signal to said coupling point.

Claim 35

A circuit unit suitable for use in the network in any of claims 10 to 24 comprising: an input for connection to said coupling unit, means coupling the address generator to said input, the state of the address generator being modified in response to address generation signals applied to said input, means for modifying the address generation signal applied to said input, output means for applying the modified address generation signal to the coupling point, monitoring means for determining whether a modified address generation signal has been applied to said input and producing an output dependent thereon, means for inhibiting the action of the modifying means in response to the output of the monitoring means, and means for controlling the address generator in response to the modified and unmodified address generation signals present at said input.

Claim 36

A circuit unit suitable for use in the network in any of claims 26 to 30, said circuit unit comprising: an input for connection to said coupling point, means coupling the address generator to said input, the state of the address generator being modified in response to address generation signals applied to said input, means for modifying the address generation signal applied to said input, and output means for applying the modified address generation signal to the coupling point, wherein the modifying means comprises means for adding one or more level transitions or pulses to the address generation signal applied to said input, wherein the address generator comprises a counter which counts the number of level transitions or pulses applied to said input, and adopting means to enable the circuit unit to adopt the state of the counter as its address.

Claim 37

The circuit unit as claimed in claim 33, comprising reset detection means for detecting a reset signal applied to said input and producing an output in response to the detection of said reset signal, an means for applying the output of the reset detection means to the address generator to reset the address generator to an initial state.

Claim 38

A circuit unit as claimed in claim 33 for use when the address generation signal comprises a carrier signal modulated by one or more level transitions or pulses or a plurality of pulses, or sets of pulses wherein the circuit unit further comprises a demodulator coupled to said input, a demodulated output being coupled to said address generator and said modifying means, a modulator for modulating a carrier signal by the modified demodulated signal and means for applying the output of the modulator to the output means.