Electrical circuit arrangement and electrical circuit unit for use in such an electrical circuit arrangement

Claim 2

An electrical circuit arrangement comprising a plurality of circuit units connected to a common path, each of the circuit units having an input for receiving a control signal and including a control circuit, said control circuit having a first input for receiving a clock signal, a second input connected to the control signal input and an output connected to an input of an address generator, said address generator being provided for generating addresses in response to said clock signal applied thereto under control of said control signal, wherein said circuit arrangement further comprises a control arrangement for generating successive control signals synchronously with the clock signal, said control arrangement having a plurality of outputs, an individual output of the control arrangement being connected to the control signal input of a respective circuit unit.

Claim 3

A circuit arrangement as claimed in claim 1 in which said control arrangement comprises a parallel output shift register, each individual output of the shift register being connected to a respective output of the control arrangement.

Claim 4

A circuit arrangement as claimed in claim 1 or claim 2, wherein at least one circuit unit comprises means for enabling the control signal input to be used for other circuit functions once the address generator has generated the address.

Claim 5

A circuit arrangement as claimed in claim 3, in which said enabling means comprises a changeover switch having its pole connected to the control signal input, a first contact connected to the second input of the control circuit and a second contact connected to a further portion of the circuit unit; and a clocked bistable circuit having an input connected to the control signal input and an output connected to a control input of the changeover switch, a change in the signal at the output of the bistable circuit being effective to cause the changeover switch to change state.

Claim 6

An electrical circuit arrangement comprising a plurality of circuit units connected to a common path, each of the circuit units having an input for receiving a control signal and including a control circuit having a first input for receiving a clock signal, a second input connected to the control signal input and an output connected to an input of an address generator, said address generator being provided for generating addresses in response to said clock signal applied thereto under control of said control signal, said circuit arrangement further comprising a control arrangement for generating successive control signals synchronously with the clock signal, said control arrangement comprising a sub-arrangement in each circuit unit, a first input of each sub-arrangement being connected to the control signal input of its respective circuit unit, said clock signal being applied to a second input of each sub-arrangement and an output of each sub-arrangement being connected to a control signal output of its respective circuit unit, each sub-arrangement being provided for generating one of said successive control signals subsequent to receipt of a control signal on its first input, the control signal output of each circuit unit being connected to the control signal input of at least one succeeding unit when present, at least one circuit unit comprising means for enabling the control signal input and the control signal output to be used for other circuit functions once the address generator has been generated the address.

Claim 7

An electrical circuit arrangement comprising a plurality of circuit units connected to a common path, each of the circuit units having an input for receiving a control signal and including a control circuit having a first input for receiving a clock signal, a second input connected to the control signal input and an output connected to an input of an address generator, said address generator being provided for generating addresses in response to said clock signal applied thereto under control of said control signal, said circuit arrangement further comprising a control arrangement for generating successive control signals synchronously with the clock signal, said control arrangement comprising a sub-arrangement in each circuit unit, a first input of each sub-arrangement being connected to the control signal input of its respective circuit unit, said clock signal being applied to a second input of each sub-arrangement and an output of each sub-arrangement being connected to a control signal output of its respective circuit unit, each sub-arrangement being provided for generating one of said successive control signals subsequent to receipt of a control signal on its first input, the control signal output of each circuit unit being connected to the control signal input of at least one succeeding unit when present, at least one circuit unit comprising means for enabling the control signal input and the control signal output to be used for other circuit functions once the address generator has been generated the address.

Claim 8

A circuit arrangement as claimed in claim 5, in which said enabling means comprises; a first changeover switch having its pole connected to the control signal input, a first contact connected to the second input of the control circuit, and a second contact connected to a further portion of the circuit unit; a second changeover switch having its pole connected to the control signal output, a first contact connected to the output of the sub-arrangement, and a second contact connected to a further portion of the circuit unit; a first clocked bistable circuit having an input connected to the control signal input and an output connected to a control input of the first changeover switch, a change in the signal at the output of the first bistable circuit being effective to cause the first changeover switch to change state; and a second clocked bistable circuit having an input connected to the output of the first bistable circuit and an output connected to a control input of the second changeover switch, a change in the signal at the output of the second bistable being effective to cause the second changeover switch to change state.

Claim 9

A circuit arrangement as claimed in claim 5, in which said enabling means comprises; a first changeover switch having its pole connected to the control signal input, a first contact connected to the second input of the control circuit, and a second contact connected to a further portion of the circuit unit; a second changeover switch having its pole connected to the control signal output, a first contact connected to the output of the sub-arrangement, and a second contact connected to a further portion of the circuit unit; and a clocked bistable circuit having an input connected to the output of the sub-arrangement and an output connected to control inputs of the first and second changeover switches, a change in the signal at the output of the bistable circuit being effective to cause the first and second changeover switches to change state.

Claim 10

A circuit arrangement as claimed in claim 5, in which the application of the clock signal to the address generator of a circuit unit is inhibited in response to the control signal applied to the control signal input of that circuit unit.

Claim 11

A circuit arrangement as claimed in claim 5, in which each sub-arrangement comprises a clocked bistable circuit having an input connected to the control signal input of its associated circuit unit, an output connected to the control signal output of its associated circuit unit, and a clock input for receiving the clock signal.

Claim 12

A circuit arrangement as claimed in claim 5, in which the control signal input of the first circuit unit is connected to an external reference potential source.

Claim 13

An electrical circuit arrangement comprising a plurality of circuit units connected to a common path and a control arrangement for generating successive control signals synchronously with a clock signal: in which each circuit unit comprises (a) a control signal input for receiving a control signal, (b) a control signal output for outputting a control signal, (c) a control circuit, (d) an address generator, and (e) a sub-arrangement of said control arrangement: wherein said control circuit has a first input for receiving said clock signal, a second input connected to said control signal input and an output connected to an input of said address generator; said address generator is provided for generating addresses in response to said clock signal, said clock signal being applied to said address generator under the control of said control signal; said sub-arrangement having a first input connected to the control signal input, a second input for receiving said clock signal, and an output connected to the control signal output, said sub-arrangement being provided for generating one of said one of said successive control signals at its output subsequent to the receipt of a control signal at its first input; and wherein the circuit units are arranged such that the control signal output of one is connected to the control signal input of the next, if present, the control arrangement is arranged to supply a signal to the control signal input of the first circuit unit, and the control circuit of each circuit unit is arranged to inhibit the application of said clock signal to the address generator when a control signal is applied to the control signal input of that circuit unit.

Claim 14

An electrical circuit arrangement comprising a plurality of circuit units connected to a common path and a control arrangement for generating successive control signals synchronously with a clock signal: in which each circuit unit comprises (a) a control signal input for receiving a control signal, (b) a control signal output for outputting a control signal, (c) a control circuit, (d) an address generator, and (e) a sub-arrangement of said control arrangement: wherein said control circuit has a first input for receiving said clock signal, a second input connected to said control signal input and an output connected to an input of said address generator; said address generator is provided for generating addresses in response to said clock signal, said clock signal being applied to said address generator under the control of said control signal; said sub-arrangement having a first input connected to the control signal input, a second input for receiving said clock signal, and an output connected to the control signal output, said sub-arrangement being provided for generating one of said one of said successive control signals at its output subsequent to the receipt of a control signal at its first input; and wherein the circuit units are arranged such that the control signal output of one is connected to the control signal input of the next, if present, the control arrangement is arranged to supply a signal to the control signal input of the first circuit unit, and the control circuit of each circuit unit is arranged to inhibit the application of said clock signal to the address generator when a control signal is applied to the control signal input of that circuit unit.

Claim 15

An electrical circuit arrangement as claimed in claim 5, in which in each circuit unit the sub-arrangement generates its control signal one period of the clock signal subsequent to the receipt of the control signal at its input.

Claim 16

A circuit arrangement as claimed in claim 11, characterized in that at least one circuit unit comprises means for enabling the control signal input and/or the control signal output to be used for other circuit functions once the address generator has generated the address.

Claim 17

A circuit arrangement as claimed in claim 5, comprising means for monitoring the state of the control signal output of the last circuit unit in the sequence.

Claim 18

A circuit arrangement as claimed in claim 14, in which said enabling means the control signal input and/or output to be used for other purposes is operable in response to a signal produced by said monitoring means.

Claim 19

A circuit arrangement as claimed in any one of claims 1, 2 and 7 to 11, characterized in that at least one circuit unit comprises means for changing the address generated by the address generator in response to appropriate signals applied to the circuit unit.

Claim 20

An electrical circuit unit for use in an electrical circuit arrangement as claimed in claim 1 or claim 2, said circuit unit comprising an input for receiving a control signal, a control circuit, and an address generator, said control circuit having a first input for receiving a clock signal, a second input connected to the control signal input and an output connected to an input of the address generator, said address generator being provided for generating addresses in response to said clock signal applied thereto under control of said control signal.

Claim 21

A circuit unit as claimed in claim 17, comprising means for enabling the control signal input to be used for other circuit functions once the address generator has generated the address.

Claim 22

An electrical circuit unit for use in an electrical circuit arrangement as claimed in claim 5, said circuit unit comprising an input for receiving a control signal, an address generator, a control circuit and a control signal output, said control circuit having a first input for receiving a clock signal, a second input connected to the control signal input and an output connected to an input of the address generator, said address generator being provided for generating addresses in response to said clock signal applied thereto under control of said control signal, said circuit unit further comprising a control sub-arrangement for generating a control signal synchronously with the clock signal, a first input of each sub-arrangement being connected to the control signal input of its respective circuit unit, said clock signal being applied to a second input of each sub-arrangement and an output of each sub-arrangement being connected to a control signal output of the respective circuit unit, the sub-arrangement being provided for generating one of said successive control signals subsequent to receipt of a control signal on its first input.

Claim 23

A circuit unit as claimed in claim 19. comprising means for enabling the control signal input and the control signal output to be used for other circuit functions once the address generator has generated the address.

Claim 24

An electrical circuit arrangement as claimed in claim 11, in which in each circuit unit the sub-arrangement generates its control signal one period of the clock signal subsequent to the receipt of the control signal at its input.

Claim 25

A circuit arrangement as claimed in claim 11, comprising means for monitoring the state of the control signal output of the last circuit unit in the sequence.

Claim 26

An electrical circuit unit for use in an electrical circuit arrangement as claimed in claim 11, said circuit unit comprising an input for receiving a control signal, an address generator, a control circuit and a control signal output, said control circuit having an first input for receiving a clock signal, a second input connected to the control signal input and an output connected to an input of the address generator, said address generator being provided for generating addresses in response to said clock signal applied thereto under control of said control signal, said circuit unit further comprising a control sub-arrangement for generating a control signal synchronously with the clock signal, a first input of each sub-arrangement being connected to the control signal input of its respective circuit unit, said clock signal being applied to a second input of each sub-arrangement and an output of each sub-arrangement being connected to a control signal output of the respective circuit unit, the sub-arrangement being provided for generating one of said successive control signals subsequent to receipt of a control signal on its first input.

Claim 27

A circuit unit as claimed in claim 23, comprising means for enabling the control signal input and the control signal output to be used for other circuit functions once the address generator has generated the address.

Claim 28

A circuit arrangement as claimed in claim 22, in which said enabling means the control signal input and/or output to be used for other purposes is operable in response to a signal produced by said monitoring means.