Fully differential non-linear amplifier

Claim 1

A fully differential non-linear amplifier which clamps its differential output signal to a constant voltage level independent of variations in process and temperature, said amplifier comprising: operation amplifier means (12) having first and second input nodes, and first and second output nodes for producing a differential output signal thereacross; a first input resistor (R1) connected between an input terminal and said first input node; a second input resistor (R2) connected between a second input terminal and said second input node; said first and second input terminal being connected to receive a differential input signal thereacross; a first feedback resistor (R3) connected between the first input node and the first output node; a second feedback resistor (R4) connected between the second input node and the second output node; a first clamping network (CN1) formed of a first P-channel clamping transistor (P10) and a first N-channel clamping transistor (N10); said first P-channel clamping transistor (P10) having its conduction path electrodes being connected between the first input node and the first output node and having its gate connected to receive a P-bias signal; said first N-channel clamping transistor (N10) having its conduction path electrodes connected between the first input node and the first output node and having its gate connected to receive an N-bias signal; a second clamping network (CN2) formed of a second P-channel clamping transistor (P12) and a second N-channel clamping transistor (N12); said second P-channel clamping transistor (P12) having its conduction path electrodes connected between the second input node and the second output node and having its gate connected to receive the P-bias signal; said second N-channel clamping transistor (N12) having its conduction path electrodes connected between the second input node and the second output node and having its gate connected to receive the N-bias signal; clamp biasing circuit means (22) being responsive to a first reference voltage (P-REFERENCE) for generating the P-bias signal and being responsive to a second reference voltage (N-REFERENCE) for generating the N-bias signal, said P-bias signal being one threshold drop below said first reference voltage, said N-bias signal being one threshold drop above said second reference voltage; and said clamp biasing circuit (22) including a P-bias circuit section (24) formed of a reference current source (IBIAS), a first current mirror arrangement (N1-N4), and a gm-connected P-channel transistor (P1), and an N-bias circuit section (26) formed of a second current mirror arrangement (N1, N2, N5, N6), a third current mirror arrangement (P2-P5), and a gm-connected N-channel transistor (N7).