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US4849366A
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Method of making a gated isolated structure
Assignee: CHUNG SHAN INSTITUTE OF SCIENCE OF TECHNOLOGY
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Filing: 1988-01-15
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Granted: 1989-07-18
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Expires: 2008-01-15
Abstract
Abstract The invention relates to a radiation hardened (R-H) bulk complementary metal oxide semiconductor (CMOS) isolation structure and a process for its formation. The isolation structure may be automatically generated from the original thin oxide layer of any commercial product by computer aided design and basically comprises a grounded MOS gate surrounding the active areas. The grounded MOS gate replaces the conventional LOCOS field oxide and consists of novel oxide-silicon nitride-oxynitride gate insulator and a CVD polysilicon film. The radiation resistance of this gated isolated structure (GIS) is suitable for application in radiation-immunity VLSI integrated circuit (≦2 μm design rule).
Inventors
- 👤 Je-Jung Hsu
- 👤 Hsing-Hai Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:19
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50; Y; Y10; Y10S; Y10S438/00; Y10S438/953
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
104 words
A process for forming a gated isolation structure in a radiation-hardened integrated circuit which comprises: implanting into a silicon substrate region a positive ion, said substrate region being free of a LOCOS field oxide, to adjust the threshold voltage of an isolated gate; forming a thin oxide layer atop the said substrate; depositing a thin silicon nitride layer on said thin oxide; thermally oxidizing the thin silicon nitride layer to form an oxynitride layer atop said silicon nitride; depositing a polysilicon layer on the said oxynitride layer; defining an isolation gate by photolithography and plasma dry etching; and thermally oxidizing the isolated gate polysilicon.
Claim 2
Dependent Claim
104 words
A process for forming a gated isolation structure in a radiation-hardened integrated circuit which comprises: implanting into a silicon substrate region a positive ion, said substrate region being free of a LOCOS field oxide, to adjust the threshold voltage of an isolated gate; forming a thin oxide layer atop the said substrate; depositing a thin silicon nitride layer on said thin oxide; thermally oxidizing the thin silicon nitride layer to form an oxynitride layer atop said silicon nitride; depositing a polysilicon layer on the said oxynitride layer; defining an isolation gate by photolithography and plasma dry etching; and thermally oxidizing the isolated gate polysilicon.
Claim 3
Dependent Claim
21 words
The process of claim 1 wherein the thin oxide, silicon nitride, and oxynitride layers are used as radiation assistance gate insulators.
Claim 4
Dependent Claim
19 words
The process of claim 1 wherein the oxynitride layer is used as an etch stopper for the polysilicon layer.
Claim 5
Dependent Claim
27 words
The process of claim 1 wherein the silicon nitride layer is used as an oxidation mask for the thin oxide region when said polysilicon layer is oxidized.
Claim 6
Dependent Claim
25 words
The process of claim 1 wherein a radiation-hardened bulk CMOS is formed which meets a process rule for less than or equal to 2 μm.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |