Timing recovery scheme for burst communication systems

Claim 2

In a circuit for receiving a bit stream in a burst mode communication system, the bit stream having a preamble portion and a data portion, a timing recovery apparatus adapted to provide a clock signal having a predetermined phase and frequency for sampling each bit of the data portion, the timing recovery apparatus comprising: detection means, arranged to receive the bit stream, for detecting the presence of a preamble portion in the bit stream, and for outputting the preamble portion and a preamble detect signal indicating the presence of a preamble portion; injection oscillator means, having an injection input, for providing the clock signal, the clock signal having a predetermined phase and frequency relationship with respect to a signal applied to the injection input; and coupling means, disposed between said detection means and said injection oscillator means, for coupling the preamble portion from said detection means directly into the injection input of said injection oscillator means when the preamble detect signal indicates the presence of a preamble portion.

Claim 3

Apparatus as recited in claim 1 wherein said injection oscillator means additionally maintains the clock signal at substantially the same frequency and phase for a period of time after the signal applied to the injection input is removed.

Claim 4

Apparatus as recited in claim 1 and additionally comprising: synchronous divider means, responsive to the clock signal from said injection oscillator means and having a clear input, for providing a plurality of output signals sub-harmonically related to the clock signal from said injection oscillator means when the clear input is inactive and for forcing the plurality of output signals to predetermined states when the clear input is active; means, fed by said detection means and driving the clear input of said synchronous divider means, for activating the clear input when the preamble detect signal output from said detection means indicates the presence of a preamble portion and for deactivating the clear input in synchronism with the termination of the presence of the preamble portion; and means, having as an output a divided clock signal, responsive to the clock signal from said injection oscillator means and the plurality of output signals from said synchronous divider means, for selecting one of such signals as the divided output signal.

Claim 5

Apparatus as recited in claim 1 wherein said coupling means comprises: delay means, coupled to said detection means, for outputting a delayed preamble portion; and means, coupled to said detection means and said delay means, for producing a frequency doubled signal having a frequency twice that of the preamble portion, and for feeding the frequency doubled signal to the injection input of said injection oscillator means.

Claim 6

In a circuit for receiving a bit stream in a burst mode communication system wherein the bit stream has a preamble portion and a data portion, a timing recovery apparatus adapted to provide a clock signal having the proper phase and frequency for sampling each bit of the data portion of the bit stream, the timing recovery apparatus comprising: frequency reference means, for outputting a reference signal; oscillator means, responsive to a first control signal, for producing an oscillator output signal having a frequency determined by the first control signal, said oscillator means further having an injection input, the oscillator output signal being phase aligned with a signal applied to the injection input; divider means, responsive to the oscillator output signal from said oscillator means, for producing the clock signal, the clock signal having a frequency equal to or sub-harmonically related to the oscillator output signal; phase detector means, responsive to the oscillator output signal from said oscillator means and the reference signal from said frequency reference means, for producing a relative phase signal indicating the relative phase between the reference signal and the oscillator output signal; filter means, responsive to the relative phase signal from said phase detector means, for producing a filtered signal; sample-and-hold means, responsive to the filtered signal from said filter means, for producing the first control signal, and for selectively sampling and holding the filtered signal; storage means, fed by said sample-and-hold means, for storing the amplitude of the first control signal and for producing a second control signal, the second control signal having substantially the same amplitude as the stored amplitude of the first control signal; subtracting means, fed by said sample-and-hold means and said storage means, for subtracting the first control signal from the second control signal to form an error signal; comparison means, fed by said subtracting means, for indicating when the error signal exceeds predetermined limits; detector means, arranged to receive the preamble portion of the bit stream, for providing a signal indicating the data rate of the data portions of the bit stream; and coupling means, coupled to said detection means and said oscillator means, for coupling the signal indicating the data rate to the injection input of said oscillator means during the preamble portion of the bit stream.

Claim 7

In a circuit for receiving a bit stream in a burst mode communication system wherein the bit stream has a preamble portion and a data portion, a timing recovery apparatus adapted to provide a clock signal having the proper phase and frequency for sampling each bit of the data portion of the bit stream, the timing recovery apparatus comprising: frequency reference means, for outputting a reference signal; oscillator means, responsive to a first control signal, for producing an oscillator output signal having a frequency determined by the first control signal, said oscillator means further having an injection input, the oscillator output signal being phase aligned with a signal applied to the injection input; divider means, responsive to the oscillator output signal from said oscillator means, for producing the clock signal, the clock signal having a frequency equal to or sub-harmonically related to the oscillator output signal; phase detector means, responsive to the oscillator output signal from said oscillator means and the reference signal from said frequency reference means, for producing a relative phase signal indicating the relative phase between the reference signal and the oscillator output signal; filter means, responsive to the relative phase signal from said phase detector means, for producing a filtered signal; sample-and-hold means, responsive to the filtered signal from said filter means, for producing the first control signal, and for selectively sampling and holding the filtered signal; storage means, fed by said sample-and-hold means, for storing the amplitude of the first control signal and for producing a second control signal, the second control signal having substantially the same amplitude as the stored amplitude of the first control signal; subtracting means, fed by said sample-and-hold means and said storage means, for subtracting the first control signal from the second control signal to form an error signal; comparison means, fed by said subtracting means, for indicating when the error signal exceeds predetermined limits; detector means, arranged to receive the preamble portion of the bit stream, for providing a signal indicating the data rate of the data portions of the bit stream; and coupling means, coupled to said detection means and said oscillator means, for coupling the signal indicating the data rate to the injection input of said oscillator means during the preamble portion of the bit stream.

Claim 8

Apparatus as recited in claim 5 wherein said storage means additionally comprises: analog-to-digital conversion means, fed by said sample-and-hold means, for converting the first control signal to a digital word; latch means, fed by said analog-to-digital conversion means, for selectively storing the digital word from the analog-to-digital conversion means; and digital-to-analog conversion means, fed by said latch means, for converting the stored digital word to the second control signal.

Claim 9

Apparatus as recited in claim 5 wherein said divider means additionally comprises: synchronous counting means, fed by the oscillator output signal from said oscillator means and having a clear input, for producing a plurality of output signals sub-harmonically related to the oscillator output signal when the clear input is inactive and forcing the plurality of output signals to predetermined states when the clear input is active; means, arranged to receive the preamble portion of the bit stream and coupled to the clear input of said synchronous counting means, for activating the clear input when the preamble portion of the bit stream is present and for disabling the clear input in synchronism with the termination of the preamble; and means responsive to the oscillator output signal from said oscillator means and the plurality of output signals from said synchronous divider means, for selecting one of such plurality of signals as the clock signal.

Claim 12

Apparatus for providing a clock signal having a predetermined phase and frequency relationship with respect to a received signal, said received signal comprising a preamble portion and a data portion, said apparatus comprising: a phase lock loop including a voltage-controlled oscillator having an injection input, for providing said clock signal, a local frequency reference for generating a reference signal, and phase detector means for providing a control signal to said oscillator indicative of the phase relationship between said clock signal and said reference signal; and means for injecting said preamble portion into said oscillator.

Claim 13

Apparatus for providing a clock signal having a predetermined phase and frequency relationship with respect to a received signal, said received signal comprising a preamble portion and a data portion, said apparatus comprising: a phase lock loop including a voltage-controlled oscillator having an injection input, for providing said clock signal, a local frequency reference for generating a reference signal, and phase detector means for providing a control signal to said oscillator indicative of the phase relationship between said clock signal and said reference signal; and means for injecting said preamble portion into said oscillator.

Claim 16

A method as in claim 10 additionally comprising: (c) detecting when the preamble portion is present; and (d) disconnecting the oscillator from the local frequency reference when the preamble portion is present.

Claim 17

A method as in claim 10 additionally comprising: (c) detecting when the clock signal has drifted more than a predetermined amount.

Claim 18

A method as in claim 10 additionally comprising: (c) synchronously dividing the clock signal to a lower frequency than the clock signal's frequency at the oscillator output