Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies

Claim 1

A parallel processor system for processing natural concurrencies in streams of low level instructions contained in a plurality of programs in said system, each of said streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system comprising: means (160) for statically adding intelligence to each instruction in each of said plurality of basic blocks for each said program, said added intelligence at least having a logical processor number (LPN) and an instruction firing time (IFT), a plurality of context files (660), each of said context files being assigned to one of said plurality of programs for processing one of said programs, each of said context files having at least a plurality of registers and condition code storage for containing processing status information, a plurality of logical resource drivers (LRDs), each logical resource driver being assigned to one of said plurality of context files, each of said logical resource drivers being receptive of said basic blocks corresponding to the program instruction stream of said assigned program from said adding means, each of said logical resource drivers comprising: (a) a plurality of queues (1730), and (b) means operative on said plurality of said basic blocks containing said intelligence from said adding means for delivering said instructions in each said basic block into said plurality of queues based on said logical processor number, said instructions in each said queue being entered according to said instruction firing time wherein the earliest instruction firing time is entered first, a plurality of individual processor elements (PEs), each of said processor elements being free of any context information, means (650) connecting said plurality of processor elements to said plurality of logical resource drivers for transferring said instruction with the earliest instruction firing time, first in said queues, from each of said logical resource drivers, in a predetermined order, to individually assigned processor elements, each said processor element having means for processing said transferred instruction, first means (670) for connecting each of said processor elements with any one of said plurality of context files, each of said processor elements having means for accessing any of a plurality of registers and condition code storage in a program's context file during the processing of the program's instruction, a plurality of memory locations (610), and second means including said logical resource drivers for connecting each of said processor elements with any one of said plurality of memory locations, each said processor element having means for accessing said memory locations during said processing of each said instruction.

Claim 24

A method for parallel processing in a plurality of processor elements natural concurrencies in streams of low level instructions contained in the programs of a plurality of users, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said method comprising the steps of: statically adding intelligence representing the natural concurrencies existing within the instructions in each basic block of the programs, said step of adding for each program comprising the steps of: (a) ascertaining the resource requirements of each instruction within each basic block to determine the natural concurrencies in each basic block, (b) identifying logical resource dependencies between instructions, (c) assigning condition code storage (CCs) to groups of resource dependent instructions, so that dependent instructions can execute on the same or different processor elements, (d) determining the earliest possible instruction firing time (IFT) for each of said instructions in each of said plurality of basic blocks, (e) adding said instruction firing times to each instruction in each of said plurality of basic blocks, (f) assigning a logical processor number (LPN) to each instruction in each of said basic blocks, (g) adding said logical processor numbers to each instruction in each of said basic blocks, and (h) repeating steps (a) through (g) until all basic blocks are processed for each of said programs, and processing the instruction having the statically added intelligence for the programs, the step of processing further comprising the steps of: (i) delivering the instructions into logical resource drivers, each said program of a user being assigned to a different logical resource driver, (j) selecting instructions from the logical resource drivers in a predetermined order based on the instruction firing time, (k) storing the selected instructions in queues of the logical resource driver based on the logical processor number, (l) generating dynamic shared context storage mapping (D-SCSM) information for each instruction, (m) selectively connecting the queues of each logical resource driver to processor elements (PEs) said queues being connected in a predetermined order so that one instruction having the earliest instruction firing time from each queue is first delivered to a given processor element, (n) processing said one instruction from each queue in each said connected processor element, (o) obtaining the input data for processing said delivered instruction from shared storage locations identified by said instruction in a context file identified by said dynamic shared context storage mapping information, (p) storing the results of said processing of said delivered instruction in shared storage identified by said dynamic information contained in said instruction, and (q) repeating steps (i) through (p) until all instructions in each of said plurality of basic blocks for all said programs are processed.

Claim 25

A method for parallel processing in a plurality of processor elements natural concurrencies in streams of low level instructions contained in the programs of a plurality of users, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said method comprising the steps of: statically adding intelligence representing the natural concurrencies existing within the instructions in each basic block of the programs, said step of adding for each program comprising the steps of: (a) ascertaining the resource requirements of each instruction within each basic block to determine the natural concurrencies in each basic block, (b) identifying logical resource dependencies between instructions, (c) assigning condition code storage (CCs) to groups of resource dependent instructions, so that dependent instructions can execute on the same or different processor elements, (d) determining the earliest possible instruction firing time (IFT) for each of said instructions in each of said plurality of basic blocks, (e) adding said instruction firing times to each instruction in each of said plurality of basic blocks, (f) assigning a logical processor number (LPN) to each instruction in each of said basic blocks, (g) adding said logical processor numbers to each instruction in each of said basic blocks, and (h) repeating steps (a) through (g) until all basic blocks are processed for each of said programs, and processing the instruction having the statically added intelligence for the programs, the step of processing further comprising the steps of: (i) delivering the instructions into logical resource drivers, each said program of a user being assigned to a different logical resource driver, (j) selecting instructions from the logical resource drivers in a predetermined order based on the instruction firing time, (k) storing the selected instructions in queues of the logical resource driver based on the logical processor number, (l) generating dynamic shared context storage mapping (D-SCSM) information for each instruction, (m) selectively connecting the queues of each logical resource driver to processor elements (PEs) said queues being connected in a predetermined order so that one instruction having the earliest instruction firing time from each queue is first delivered to a given processor element, (n) processing said one instruction from each queue in each said connected processor element, (o) obtaining the input data for processing said delivered instruction from shared storage locations identified by said instruction in a context file identified by said dynamic shared context storage mapping information, (p) storing the results of said processing of said delivered instruction in shared storage identified by said dynamic information contained in said instruction, and (q) repeating steps (i) through (p) until all instructions in each of said plurality of basic blocks for all said programs are processed.

Claim 29

A method for parallel processing natural concurrencies in streams of low level instructions contained in the programs of a plurality of users located in a system having a plurality of processor elements and shared storage locations, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said method comprising the steps of: statically adding intelligence to the instructions in each basic block of the programs, said added intelligence identifying the natural concurrencies within each basic block, said added intelligence having a least an instruction firing time (IFT) and a logical processor number (LPN), and processing the instructions having the statically added intelligence for executing the programs, the step of processing further comprising the steps of: (a) delivering the instructions into the system, each said user being assigned to a different context file in said system, (b) dynamically generating shared context state mapping (D-SCSM) information for each instruction identifying said context file containing shared storage locations, (c) separately storing the delivered instructions in the system based on the logical processor number (LPN), (d) selectively connecting the separately stored instructions to the processor elements assigned to the logical processor number for the instructions, said separately stored instructions being delivered in a predetermined order so that one instruction having the earliest instruction firing time from each of the separately stored instructions is delivered to a given processor element, (e) processing said one instruction from each connected separately stored instructions in each said connected processor element, (f) obtaining the input data for processing said connected instruction from a shared storage location identified at least in part by said shared context storage mapping information, (g) storage the results of said processing of said connected instruction in a shared storage location identified in part by said shared context storage mapping information, and (h) repeating steps (a) through (g) until all instructions of each of said plurality of basic blocks for all of said programs are processed.

Claim 30

A method for parallel processing natural concurrencies in streams of low level instructions contained in the programs of a plurality of users located in a system having a plurality of processor elements and shared storage locations, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said method comprising the steps of: statically adding intelligence to the instructions in each basic block of the programs, said added intelligence identifying the natural concurrencies within each basic block, said added intelligence having a least an instruction firing time (IFT) and a logical processor number (LPN), and processing the instructions having the statically added intelligence for executing the programs, the step of processing further comprising the steps of: (a) delivering the instructions into the system, each said user being assigned to a different context file in said system, (b) dynamically generating shared context state mapping (D-SCSM) information for each instruction identifying said context file containing shared storage locations, (c) separately storing the delivered instructions in the system based on the logical processor number (LPN), (d) selectively connecting the separately stored instructions to the processor elements assigned to the logical processor number for the instructions, said separately stored instructions being delivered in a predetermined order so that one instruction having the earliest instruction firing time from each of the separately stored instructions is delivered to a given processor element, (e) processing said one instruction from each connected separately stored instructions in each said connected processor element, (f) obtaining the input data for processing said connected instruction from a shared storage location identified at least in part by said shared context storage mapping information, (g) storage the results of said processing of said connected instruction in a shared storage location identified in part by said shared context storage mapping information, and (h) repeating steps (a) through (g) until all instructions of each of said plurality of basic blocks for all of said programs are processed.

Claim 31

A method for parallel processing, in a system, natural concurrencies in streams of low level instructions contained in a program, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system having a plurality of processor elements and a plurality of shared storage locations, said method comprising the steps of: statically adding intelligence representing the natural concurrencies existing within the instructions in each basic block, said step of adding comprising the steps of: (a) ascertaining the resource requirements of each instruction within each basic block to determine the natural concurrencies in each basic block, (b) identifying logical resource dependencies between instructions, (c) assigning condition code storage (CCs) to groups of resource dependent instructions, such that dependent instructions can execute on the same of different processor elements, (d) determining the earliest possible instruction firing time (IFT) for each of said instructions in each of said plurality of basic blocks, (e) adding said instruction firing times to each instruction in each of said plurality of basic blocks, (f) assigning a logical processor number (LPN) to each instruction in each of said basic blocks, (g) adding said logical processor numbers to each instruction in each of said basic blocks, and (h) repeating steps (a) through (g) until all basic blocks are processed for said program, and processing the instructions having the statically added intelligence in the system, the step of processing further comprising the steps of: (i) separately storing instructions delivered in the system based on the logical processor number, (j) selectively connecting the separately stored instructions to the processor element (PE) assigned to the logical processor number, said separately stored instructions being delivered in a predetermined order so that one instruction having the earliest instruction firing time is connected to a given processor element, (k) processing said one instruction from each of the separately stored instructions in each said connected processor element, and (l) repeating steps (i) through (k) until all instructions in each of said plurality of basic blocks for said program are processed.

Claim 32

A method for parallel processing, in a system, natural concurrencies in streams of low level instructions contained in a program, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system having a plurality of processor elements and a plurality of shared storage locations, said method comprising the steps of: statically adding intelligence representing the natural concurrencies existing within the instructions in each basic block, said step of adding comprising the steps of: (a) ascertaining the resource requirements of each instruction within each basic block to determine the natural concurrencies in each basic block, (b) identifying logical resource dependencies between instructions, (c) assigning condition code storage (CCs) to groups of resource dependent instructions, such that dependent instructions can execute on the same of different processor elements, (d) determining the earliest possible instruction firing time (IFT) for each of said instructions in each of said plurality of basic blocks, (e) adding said instruction firing times to each instruction in each of said plurality of basic blocks, (f) assigning a logical processor number (LPN) to each instruction in each of said basic blocks, (g) adding said logical processor numbers to each instruction in each of said basic blocks, and (h) repeating steps (a) through (g) until all basic blocks are processed for said program, and processing the instructions having the statically added intelligence in the system, the step of processing further comprising the steps of: (i) separately storing instructions delivered in the system based on the logical processor number, (j) selectively connecting the separately stored instructions to the processor element (PE) assigned to the logical processor number, said separately stored instructions being delivered in a predetermined order so that one instruction having the earliest instruction firing time is connected to a given processor element, (k) processing said one instruction from each of the separately stored instructions in each said connected processor element, and (l) repeating steps (i) through (k) until all instructions in each of said plurality of basic blocks for said program are processed.

Claim 33

A method for parallel processing, in a system, natural concurrencies in streams of low level instructions contained in a program, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system having a plurality of processor elements and a plurality of shared storage locations, said method comprising the steps of: statically adding intelligence representing the natural concurrencies existing within the instructions in each basic block, said step of adding comprising the steps of: (a) determining the earliest possible instruction firing time (IFT) for each of said instructions in each of said plurality of basic blocks, (b) adding said instruction firing times to each instruction in each of plurality of basic blocks, (c) assigning a logical processor number (LPN) to each instruction in each of said basic blocks, and (d) adding said logical processor numbers to each instruction in each of said basic blocks, and processing the instructions having the statically added intelligence, the step of processing further comprising the steps of: (e) separately storing instructions delivered in the system based on the logical processor number, (f) selectively connecting said separately stored instructions to processor elements (PEs) assigned to a given logical processor number, said instructions connected in a predetermined order so that one instruction having the earliest instruction firing time from each of said separately stored instructions is connected to a given processor element, (g) processing said one connected instruction in each said connected processor element, (h) obtaining the input data for processing said connected instruction from a shared storage location identified by said instruction, (i) storing the results of said processing of said connected instruction in a shared storage location identified by said instruction, and (j) repeating steps (e) through (i) until all instructions are processed in each of said plurality of basic blocks for said program.

Claim 34

A method for parallel processing, in a system, natural concurrencies in streams of low level instructions contained in a program, each of the streams having a plurality of single entry-single exit (SESE) basic blocks (BBs), said system having a plurality of processor elements and a plurality of shared storage locations, said method comprising the steps of: statically adding intelligence representing the natural concurrencies existing within the instructions in each basic block, said step of adding comprising the steps of: (a) determining the earliest possible instruction firing time (IFT) for each of said instructions in each of said plurality of basic blocks, (b) adding said instruction firing times to each instruction in each of plurality of basic blocks, (c) assigning a logical processor number (LPN) to each instruction in each of said basic blocks, and (d) adding said logical processor numbers to each instruction in each of said basic blocks, and processing the instructions having the statically added intelligence, the step of processing further comprising the steps of: (e) separately storing instructions delivered in the system based on the logical processor number, (f) selectively connecting said separately stored instructions to processor elements (PEs) assigned to a given logical processor number, said instructions connected in a predetermined order so that one instruction having the earliest instruction firing time from each of said separately stored instructions is connected to a given processor element, (g) processing said one connected instruction in each said connected processor element, (h) obtaining the input data for processing said connected instruction from a shared storage location identified by said instruction, (i) storing the results of said processing of said connected instruction in a shared storage location identified by said instruction, and (j) repeating steps (e) through (i) until all instructions are processed in each of said plurality of basic blocks for said program.

Claim 35

A method for parallel processing natural concurrencies in a program in a system having a plurality of processor elements (PEs), said processor element having access to input data located in a plurality of shared resource locations, said program having a plurality of single entry-single exit (SESE) basic blocks (BBs) with each of said basic blocks (BBs) having a stream of instructions, said method comprising the steps of: ascertaining the resource requirements of each instruction within each of said basic blocks, identifying logical resource dependencies between instructions, assigning condition code storage (CCs) to groups of resource dependent instructions, such that dependent instructions can execute on the same of different processor elements, determining the earliest possible instruction firing time (IFT) for each of the instructions in said plurality of basic blocks, adding said instruction firing times (IFTs) to each instruction in each of said plurality of basic blocks in response to said determination, assigning a logical processor number (LPN) to each instruction in each of said basic blocks, adding said assigned logical processor number (LPN) to each instruction in each of said plurality of basic blocks in response to said assignment, separately storing the instructions, with said added instruction firing time and said added logical processor numbers, based on the logical processor number, each group of said separately stored instructions containing instructions having only the same logical processor number, selectively connecting said separately stored instructions to said processor elements based on the logical processor number, and each said processor element receiving the instruction in said connected group having the earliest instruction firing time first, said processor element having means for performing the steps of: (a) obtaining input data for processing said received instruction from a shared storage location in said plurality of shared resource locations identified by said instruction, (b) storing the results based upon the aforesaid step of processing in a shared storage location in said plurality of shared resource locations identified by said received instruction, and (c) repeating the aforesaid steps (a) and (b) for the next received instruction until all instructions are processed.

Claim 36

A method for parallel processing natural concurrencies in a program in a system having a plurality of processor elements (PEs), said processor element having access to input data located in a plurality of shared resource locations, said program having a plurality of single entry-single exit (SESE) basic blocks (BBs) with each of said basic blocks (BBs) having a stream of instructions, said method comprising the steps of: ascertaining the resource requirements of each instruction within each of said basic blocks, identifying logical resource dependencies between instructions, assigning condition code storage (CCs) to groups of resource dependent instructions, such that dependent instructions can execute on the same of different processor elements, determining the earliest possible instruction firing time (IFT) for each of the instructions in said plurality of basic blocks, adding said instruction firing times (IFTs) to each instruction in each of said plurality of basic blocks in response to said determination, assigning a logical processor number (LPN) to each instruction in each of said basic blocks, adding said assigned logical processor number (LPN) to each instruction in each of said plurality of basic blocks in response to said assignment, separately storing the instructions, with said added instruction firing time and said added logical processor numbers, based on the logical processor number, each group of said separately stored instructions containing instructions having only the same logical processor number, selectively connecting said separately stored instructions to said processor elements based on the logical processor number, and each said processor element receiving the instruction in said connected group having the earliest instruction firing time first, said processor element having means for performing the steps of: (a) obtaining input data for processing said received instruction from a shared storage location in said plurality of shared resource locations identified by said instruction, (b) storing the results based upon the aforesaid step of processing in a shared storage location in said plurality of shared resource locations identified by said received instruction, and (c) repeating the aforesaid steps (a) and (b) for the next received instruction until all instructions are processed.

Claim 39

A method for parallel processing instructions of a program having natural concurrencies with a plurality of processor elements (PEs), said processor elements having access to input data located in a plurality of shared resource locations, said program having a plurality of single entry-single exit (SESE) basic blocks (BBs) with each of said basic blocks (BBs) having a stream of method instructions, said method comprising the steps of: ascertaining the resource requirements of each instruction within each of said basic blocks, identifying logical resource dependencies between instructions, assigning condition code storage (CCs) to groups of resource dependent instructions, such that dependent instructions can execute on the same or different processor elements, determining the earliest possible instruction firing time (IFT) for each of the instructions in each of said plurality of basic blocks, adding said instruction firing times to each instruction in each of said plurality of basic blocks in response to said determination, assigning a logical processor number (LPN) to each instruction in each of said basic blocks, adding said assigned logical processor number to each instruction in each of said plurality of basic blocks in response to said assignment, forming execution sets (ESs) of basic blocks in response to said steps of adding said instruction firing times and logical processor numbers, (i) separately storing the instructions contained within a given formed execution set based on the logical processor number, each group of said separately stored instructions containing instructions having only the same logical processor number, (ii) selectively connecting said separately stored instructions to said processor elements elements based on the logical processor number, (iii) each said processor element receiving the instruction having the earliest instruction firing time (IFT) first, said processor element having means for performing the steps of: (a) obtaining input data for processing said received instruction from a shared storage location in said plurality of shared resource locations as identified by said instruction, (b) storing the results based upon the aforesaid step of processing in a shared storage location in said plurality of shared resource locations as identified by said instruction, (c) repeating the aforesaid steps (a) and (b) for the next received instruction until all instructions are processed, and (iv) repeating the aforesaid steps (i) through (iii) for all execution sets that are processed.

Claim 40

A method for parallel processing instructions of a program having natural concurrencies with a plurality of processor elements (PEs), said processor elements having access to input data located in a plurality of shared resource locations, said program having a plurality of single entry-single exit (SESE) basic blocks (BBs) with each of said basic blocks (BBs) having a stream of method instructions, said method comprising the steps of: ascertaining the resource requirements of each instruction within each of said basic blocks, identifying logical resource dependencies between instructions, assigning condition code storage (CCs) to groups of resource dependent instructions, such that dependent instructions can execute on the same or different processor elements, determining the earliest possible instruction firing time (IFT) for each of the instructions in each of said plurality of basic blocks, adding said instruction firing times to each instruction in each of said plurality of basic blocks in response to said determination, assigning a logical processor number (LPN) to each instruction in each of said basic blocks, adding said assigned logical processor number to each instruction in each of said plurality of basic blocks in response to said assignment, forming execution sets (ESs) of basic blocks in response to said steps of adding said instruction firing times and logical processor numbers, (i) separately storing the instructions contained within a given formed execution set based on the logical processor number, each group of said separately stored instructions containing instructions having only the same logical processor number, (ii) selectively connecting said separately stored instructions to said processor elements elements based on the logical processor number, (iii) each said processor element receiving the instruction having the earliest instruction firing time (IFT) first, said processor element having means for performing the steps of: (a) obtaining input data for processing said received instruction from a shared storage location in said plurality of shared resource locations as identified by said instruction, (b) storing the results based upon the aforesaid step of processing in a shared storage location in said plurality of shared resource locations as identified by said instruction, (c) repeating the aforesaid steps (a) and (b) for the next received instruction until all instructions are processed, and (iv) repeating the aforesaid steps (i) through (iii) for all execution sets that are processed.

Claim 41

A system for parallel processing natural concurrencies in a program, said program having a plurality of single entry-singe exit (SESE) basic blocks (BBs) wherein each of said basic blocks contains a stream of instructions, said system comprising: means (160) receptive of said plurality of basic blocks for determining said natural concurrencies within said instruction stream for each of said basic blocks, said determining means further having means for adding timing and processor information to each instruction in response to said determined natural concurrencies so that all processing resources required by any given instruction are allocated in advance of program execution, means (620) receiving said basic blocks (BBs) of instructions having said added timing and processor information for storing said received instructions, a plurality of processor elements (PEs), means (650) for selectively connecting said plurality of processor elements to said storing means, a plurality of shared resource (660), means (670) for selectively interconnecting said plurality of processor elements (PEs) with said plurality of shared resources (660), said storing means having means for delivering instructions in order of the earliest firing time first, based upon said firing timing information, to the processor elements over said connecting means and into said processor elements, and said processor elements having means for processing each received instruction from said storing means (620), said processor elements being connected to the shared resources identified by each said instruction and wherein all resource information and context information pertaining to said instruction are each stored in one of said plurality of shared resources and said storing means (620).

Claim 42

A system for parallel processing natural concurrencies in a program, said program having a plurality of single entry-singe exit (SESE) basic blocks (BBs) wherein each of said basic blocks contains a stream of instructions, said system comprising: means (160) receptive of said plurality of basic blocks for determining said natural concurrencies within said instruction stream for each of said basic blocks, said determining means further having means for adding timing and processor information to each instruction in response to said determined natural concurrencies so that all processing resources required by any given instruction are allocated in advance of program execution, means (620) receiving said basic blocks (BBs) of instructions having said added timing and processor information for storing said received instructions, a plurality of processor elements (PEs), means (650) for selectively connecting said plurality of processor elements to said storing means, a plurality of shared resource (660), means (670) for selectively interconnecting said plurality of processor elements (PEs) with said plurality of shared resources (660), said storing means having means for delivering instructions in order of the earliest firing time first, based upon said firing timing information, to the processor elements over said connecting means and into said processor elements, and said processor elements having means for processing each received instruction from said storing means (620), said processor elements being connected to the shared resources identified by each said instruction and wherein all resource information and context information pertaining to said instruction are each stored in one of said plurality of shared resources and said storing means (620).

Claim 50

A system for parallel processing natural concurrencies in a program, said program having a plurality of single entry-single exit (SESE) basic blocks (BBs) wherein each of said basic blocks (BBs) contains a stream of instructions, said system comprising: means (160) receptive of said plurality of basic blocks for determining said natural concurrencies within said instruction stream for each of said basic blocks, said determining means further having means for adding timing, processor, and resource access information to each instruction in response to said determined natural concurrencies so that all processing resources required by any given instruction are allocated in advance of instruction execution, said determining means further having means for forming basic blocks into execution set (ESs) containing said added instruction firing times and logical processor numbers, wherein branches from any given basic block within a given execution set out of said given execution set to a basic block in another execution set is statistically minimized, means (620) receptive of said execution sets having said added information for storing said instructions, a plurality of context-free processor elements connected to said storing means, and a plurality of shared resources connected to said plurality of context-free processor elements, said processor elements having means for processing its instructions based upon said processor number, timing, and resource access information from said storing means, said processor elements having means for obtaining all necessary context data from said plurality of shared resources based upon location data set forth in said instructions for processing said instruction and having means for delivering all necessary context data to said plurality of shared resources at locations based upon and identified in said instructions.

Claim 51

A system for parallel processing natural concurrencies in a program, said program having a plurality of single entry-single exit (SESE) basic blocks (BBs) wherein each of said basic blocks (BBs) contains a stream of instructions, said system comprising: means (160) receptive of said plurality of basic blocks for determining said natural concurrencies within said instruction stream for each of said basic blocks, said determining means further having means for adding timing, processor, and resource access information to each instruction in response to said determined natural concurrencies so that all processing resources required by any given instruction are allocated in advance of instruction execution, said determining means further having means for forming basic blocks into execution set (ESs) containing said added instruction firing times and logical processor numbers, wherein branches from any given basic block within a given execution set out of said given execution set to a basic block in another execution set is statistically minimized, means (620) receptive of said execution sets having said added information for storing said instructions, a plurality of context-free processor elements connected to said storing means, and a plurality of shared resources connected to said plurality of context-free processor elements, said processor elements having means for processing its instructions based upon said processor number, timing, and resource access information from said storing means, said processor elements having means for obtaining all necessary context data from said plurality of shared resources based upon location data set forth in said instructions for processing said instruction and having means for delivering all necessary context data to said plurality of shared resources at locations based upon and identified in said instructions.