Patent US4847616A successfully refreshed from Google Patents.
US4847616A
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Mode selection circuit
Assignee: NEC Corp
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Filing: 1988-08-24
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Granted: 1989-07-11
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Expires: 2008-08-24
Abstract
Abstract A mode selection circuit for supplying a mode selection signal and a reset signal to an apparatus having a plurality of operating modes each time an operating mode is selected includes a mode switch to which the operating mode is manually set, a mode register for outputting data representing the operating mode designated by a software command, a first AND gate for receiving outputs from the mode switch and the mode register and supplying an output to the apparatus as the mode selection signal, a first reset signal generator for generating a first reset signal in accordance with one of a power switch and a reset switch, a second reset signal generator for generating a second reset signal designated by the software command, and a second AND gate for selecting one of the first and second reset signals and outputting the selected signal to the apparatus as the reset signal.
Inventors
- 👤 Yutaka Gotou
- 👤 Kiyotaka Matsubara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:49
CPC Classifications
G; G04; G04G; G04G5/00; G04C; G04C10/00; G04C10/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
193 words
A mode selection circuit for supplying a mode selection signal and a reset signal to an apparatus having a plurality of operating modes each time an operating mode is selected, said mode selection circuit comprising: a mode switch to which said operating mode is manually set; a power switch and a reset switch, both to be manually set; reset signal generating means for generating a first reset signal in accordance with one of said power switch and said reset switch; mode register means for outputting a signal representing a desired operating mode in accordance with a command signal; pseudo reset signal generating means for generating a second reset signal in accordance with said command signal; first gate means for selecting a selected output from either said mode switch or from said mode register means, and for outputting said selected output to said apparatus as said mode selection signal; and second gate means for selecting one of said first and said second reset signals from said reset signal generating means and said pseudo signal generating means respectively and for outputting said selected first or second reset signal to said apparatus as said reset signal.
Claim 2
Dependent Claim
193 words
A mode selection circuit for supplying a mode selection signal and a reset signal to an apparatus having a plurality of operating modes each time an operating mode is selected, said mode selection circuit comprising: a mode switch to which said operating mode is manually set; a power switch and a reset switch, both to be manually set; reset signal generating means for generating a first reset signal in accordance with one of said power switch and said reset switch; mode register means for outputting a signal representing a desired operating mode in accordance with a command signal; pseudo reset signal generating means for generating a second reset signal in accordance with said command signal; first gate means for selecting a selected output from either said mode switch or from said mode register means, and for outputting said selected output to said apparatus as said mode selection signal; and second gate means for selecting one of said first and said second reset signals from said reset signal generating means and said pseudo signal generating means respectively and for outputting said selected first or second reset signal to said apparatus as said reset signal.
Claim 3
Dependent Claim
157 words
A mode selection circuit for supplying a mode selection signal and a reset signal to an apparatus having a plurality of operating modes each time an operating mode is selected, said mode selection circuit comprising: a mode switch to which an operating mode is manually set; mode register means for outputting data representing an operating mode designated by a software command; a first AND gate receiving outputs from said mode switch and said mode register means and supplying an output to said apparatus as said mode selection signal; first reset signal generating means for generating a first reset signal in accordance with one of a power switch and a reset switch; second reset signal generating means for generating a second reset signal designated by said software command; and a second AND gate selecting one of the first and second reset signals and outputting said selected first or second reset signal to said apparatus as said reset signal.
Claim 4
Dependent Claim
157 words
A mode selection circuit for supplying a mode selection signal and a reset signal to an apparatus having a plurality of operating modes each time an operating mode is selected, said mode selection circuit comprising: a mode switch to which an operating mode is manually set; mode register means for outputting data representing an operating mode designated by a software command; a first AND gate receiving outputs from said mode switch and said mode register means and supplying an output to said apparatus as said mode selection signal; first reset signal generating means for generating a first reset signal in accordance with one of a power switch and a reset switch; second reset signal generating means for generating a second reset signal designated by said software command; and a second AND gate selecting one of the first and second reset signals and outputting said selected first or second reset signal to said apparatus as said reset signal.
Claim 5
Dependent Claim
56 words
A mode selection circuit according to claim 2, wherein said mode register means and said second reset signal generating means comprise timing means for generating a common timing signal in accordance with said software command, said timing means enabled to receive said software command in accordance with said reset signal output from said second AND gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |